Question

1. Design a synchronous counter of Mod 5 of three inputs (q1, q2, q3) using a negative edge triggered JK flip flop that goes through the following sequence figure 1. Show the design steps using the excitation table of JK flip-flop, circuit excitation table, K-map reduction, and circuit diagram. (30 Marks) 000 100 001 011 010 Figure 1 2. a) Implement the Boolean function $f(A, B, C) = \sum(1,2,3,7)$ using 1:8 De-Multiplexer. (10 Marks) b) The logic diagram shown in figure 2 shows the 2 to 1 MUX. What will be the Boolean expression of Z in the given diagram? (10 Marks) D Z D' Y Figure 2

          1. Design a synchronous counter of Mod 5 of three inputs (q1, q2, q3) using a negative edge
triggered JK flip flop that goes through the following sequence figure 1. Show the design steps
using the excitation table of JK flip-flop, circuit excitation table, K-map reduction, and circuit
diagram.
(30 Marks)
000
100
001
011
010
Figure 1
2.
a) Implement the Boolean function $f(A, B, C) = \sum(1,2,3,7)$ using 1:8 De-Multiplexer.
(10 Marks)
b) The logic diagram shown in figure 2 shows the 2 to 1 MUX. What will be the Boolean
expression of Z in the given diagram?
(10 Marks)
D
Z
D'
Y
Figure 2

1. Design a synchronous counter of Mod 5 of three inputs (q1, q2, q3) using a negative edge
triggered JK flip flop that goes through the following sequence figure 1. Show the design steps
using the excitation table of JK flip-flop, circuit excitation table, K-map reduction, and circuit
diagram.
(30 Marks)
000
100
001
011
010
Figure 1
2.
a) Implement the Boolean function f(A, B, C) = ∑(1,2,3,7) using 1:8 De-Multiplexer.
(10 Marks)
b) The logic diagram shown in figure 2 shows the 2 to 1 MUX. What will be the Boolean
expression of Z in the given diagram?
(10 Marks)
D
Z
D'
Y
Figure 2

Added by Daniel S.

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