12. Draw the logic diagram of a four-bit register with four...

12. Draw the logic diagram of a four-bit register with four D flip-flops and four 4 imes 1 multiplexers with mode selection inputs $s_1$ and $s_0$. The register operates according to the following function table. $S_1$|$S_0$ |Register Operation ---|---|--- 0|0|2's complement 0|1|Synchronous reset with the clock 1|0|Resetting 2 LSB bits and leave the rest unchanged 1|1|Setting 2 LSB bits and leave the rest unchanged

Transcript

00:01 Hello students, here in the quotient it says to draw a 4d flip -flop and 4, 4x3 multiplexer.

00:10 So, first we draw a 4x3 multiplexer as this is first multiplexer, this is second multiplexer, this is third multiplexer and at last this is the fourth multiplexer.

00:43 Here we will draw firstly two selection lines s0 and s1 and four input ports 0, 1, 2 and 3.

01:09 Similarly in all s0, s1, 0, 1, 2 and 3, two select line s0, s1, four input lines 0, 1, 2 and 3 and similarly in the last multiplexer s0, s1, 0, 1, 2 and 3.

01:38 Here we will have one output port that is y in all the multiplexers, this again is y.

01:49 Next we will draw the respective flip -flops, the d flip -flops.

01:55 For the first this is d flip -flop, for the second one again this is the second d flip -flop, this will be the third d flip -flop and this one is the fourth d flip -flop.

02:22 Now this output of the multiplexer will be connected to the input of the d flip -flop and here we will have two outputs q and q'.

02:41 This is the normal output and this is the complemented output.

02:48 Here again input q and q complement, these are the outputs.

03:01 Here again one normal output and one normal and one complement.

03:12 Similarly here one normal input, sorry normal output and one normal output.

03:23 Now the question says to give the synchronous input of clock pulses...

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