Question

1a) D-type FF 74LVC2G74. Suppose the clock is 75.2 MHz. What is the minimum duty cycle of the clock? Assume Vcc = 3.3V. The answer is 20%. What are the steps to get to this answer? 1b) What is the setup time for this FF? Assume Vcc = 3.3V. The answer is 1.3 ns. What are the steps to get to this answer? 1c) What is the propagation delay to reset Q output when the clear input is asserted? Assume Vcc = 2.5 V. The answer is 7 ns. What are the steps to get to this answer? 

          1a) D-type FF 74LVC2G74. Suppose the clock is 75.2 MHz. What is the minimum duty cycle of the clock? Assume Vcc = 3.3V. The answer is 20%. What are the steps to get to this answer? 
    1b) What is the setup time for this FF? Assume Vcc = 3.3V. The answer is 1.3 ns. What are the steps to get to this answer?
    1c) What is the propagation delay to reset Q output when the clear input is asserted? Assume Vcc = 2.5 V. The answer is 7 ns. What are the steps to get to this answer?
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University Physics with Modern Physics
University Physics with Modern Physics
Hugh D. Young 14th Edition
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1a) D-type FF 74LVC2G74. Suppose the clock is 75.2 MHz. What is the minimum duty cycle of the clock? Assume Vcc = 3.3V. The answer is 20%. What are the steps to get to this answer? 1b) What is the setup time for this FF? Assume Vcc = 3.3V. The answer is 1.3 ns. What are the steps to get to this answer? 1c) What is the propagation delay to reset Q output when the clear input is asserted? Assume Vcc = 2.5 V. The answer is 7 ns. What are the steps to get to this answer?
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Transcript

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00:01 Here when we talk about the function of dff, so it is rising edge or falling edge of clock, rising or falling edge of clock and input d goes to the output and above waveform it is clear that rising edge of clk2 output q, this is equal to d and when we talk about when clk1, this is equal to 0, so here the d passes to qm...
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