Question

3. (20 pts) Two submodules partA and partB have been designed as two Verilog files partA.v and partB.v, readily available for use. d[2] d[1] d[0] w[2] w[1] w[0] module partA (x, y, d); input x, y; output reg [2:0] d; endmodule module partB(w,s); input [2:0] w; output s; endmodule The diagram of mycircuit is shown in Fig.2. Write a Verilog file for the top module part of module mycircuit by instantiating modules partA and partB. Use the signal names in the diagram for your Verilog codes. (20 points) X[1] t[2] x d[2] w[2] d[1] t[1] w[1] F S X[0] y d[0] w[0] t[0] Fig.2 mycircuit

          3. (20 pts)
Two submodules partA and partB have been designed as two Verilog files partA.v and
partB.v, readily available for use.
d[2]
d[1]
d[0]
w[2]
w[1]
w[0]
module partA (x, y, d);
input x, y;
output reg [2:0] d;
endmodule
module partB(w,s);
input [2:0] w;
output s;
endmodule
The diagram of mycircuit is shown in Fig.2. Write a Verilog file for the top module part of
module mycircuit by instantiating modules partA and partB. Use the signal names in the
diagram for your Verilog codes. (20 points)
X[1]
t[2]
x d[2]
w[2]
d[1] t[1]
w[1]
F
S
X[0]
y d[0]
w[0]
t[0]
Fig.2 mycircuit

3. (20 pts)
Two submodules partA and partB have been designed as two Verilog files partA.v and
partB.v, readily available for use.
d[2]
d[1]
d[0]
w[2]
w[1]
w[0]
module partA (x, y, d);
input x, y;
output reg [2:0] d;
endmodule
module partB(w,s);
input [2:0] w;
output s;
endmodule
The diagram of mycircuit is shown in Fig.2. Write a Verilog file for the top module part of
module mycircuit by instantiating modules partA and partB. Use the signal names in the
diagram for your Verilog codes. (20 points)
X[1]
t[2]
x d[2]
w[2]
d[1] t[1]
w[1]
F
S
X[0]
y d[0]
w[0]
t[0]
Fig.2 mycircuit

Added by Oscar S.

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