4.6 Section 4.4 does not discuss I-type instructions like ADDI or ANDI.
4.6.1 What additional logic blocks, if any, are needed to add I-type instructions to the CPU shown in Figure 4.23? Add any necessary logic blocks to Figure 4.23 and explain their purpose.
4.6.2 List the values of the signals generated by the control unit for ADDI. Explain the reasoning for any "don't care" control signals.
ALU Add result
Reg2Loc Uncondbranch Branch MemRead Instruction [31-21] MemtoReg Control ALUOp MemWrite ALUSrc RegWrite
Shift left 2
Instruction [9-5] Read Instruction [20-16] register 1 Read Read data 1 register 2 Write Read register data 2 Instruction [4-0] Write data Registers
Read address
Instruction [31-0] Instruction memory
Zero ALU ALU result
Read Address data
Data Write data memory
Instruction [31-0]
32 Sign- 64 extend
ALU control
Instruction [31-21]