7) 12 pts. A non-pipelined system takes 100ns to process a task. The same task can be processed in a 5-segment pipeline with a clock cycle of 20ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the theoretical speedup that could be achieved with this pipeline system over the non-pipelined system? a) Determine the speedup ratio of the pipeline for 100 tasks. b) Determine the speedup ratio of the pipeline for 20 tasks. c) Determine the speedup ratio of the pipeline for 1 task. d) What is the maximum speed up that could be achieved with the pipeline unit over the non-pipelined unit? 8) 8 pts - Suppose we have the instruction Load 500 Assume R1 = 200 and is implied in the indexed addressing mode. Given the memory values below, determine the actual value loaded into the accumulator register using: immediate, direct, indirect, and indexed addressing modes. Address Value 100 600 ... 400 300 ... 500 100 ... 600 500 ... 700 800 Mode Value Immediate Direct Indirect Indexed
Added by Alice J.
Close
Step 1
The pipelined system takes 20ns per clock cycle and has 5 segments, so it can process one task in 20 x 5 = 100ns. Show more…
Show all steps
Your feedback will help us improve your experience
Sri K and 67 other AP CS educators are ready to help you.
Ask a new question
Labs
Want to see this concept in action?
Explore this concept interactively to see how it behaves as you change inputs.
Key Concepts
Recommended Videos
In this question, we examine how data dependencies affect execution in the basic 5-stage pipeline for the code below: sub $t0, $t1, $t5 lw $t0, 0($t1) add $t2, $t0, $t6 add $t7, $t2, $t0 Assume the following cycle times for each of the without forwarding and full forwarding. a. Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to eliminate them and rewrite these instructions with the NOP instructions in your answer. b. Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them and rewrite these instructions with the NOP instructions in your answer. c. Assume there is ALU-ALU forwarding. Indicate hazards and add NOP instructions to eliminate them and rewrite these instructions with the NOP instructions in your answer. d. What is the total execution time of this instruction sequence without forwarding and with full forwarding? What is the speedup achieved by adding full forwarding to a pipeline that had no forwarding? Note: Speedup is not the difference in two timings. Consider two execution times t1 = 200 ns and t2 = 150 ns. The speedup is the ratio of Higher Time (Slower Execution) / Lower Time (Faster Execution). Thus, speedup = 200/150 (Unit needs to be the same - in this case, nanoseconds) = 1.33 Without Forwarding With Full Forwarding 250 ps 300 ps
Akash M.
Adi S.
We examine how pipelining affects the clock cycle time of the processor. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: ALU/Logic Branch LDUR STUR 45% 20% 20% 15% a) What is the clock cycle time in a pipelined and non-pipelined processor? b) What is the total latency of an LDUR instruction in a pipelined and non-pipelined processor? c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? d) Assuming there are no stalls or hazards, what is the utilization of the data memory? e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit?
Maitreya E.
Recommended Textbooks
Computer Science and Information Technology
Introduction to Programming Using Python
Computer Science - An Overview
Transcript
Watch the video solution with this free unlock.
EMAIL
PASSWORD