Question

A CMOS inverter with minimum sized transistors has k_n =0.2mA/V^2, k_p = 0.1mA/V^2 and V_{tn}=|V_{tp}|=0.6V. Assume V_{DD} = 3.3V. a) What is the inverter gate switching threshold voltage V_{th}? b) What is the resistance for each transistors using our general expression for MOSFET resistance in saturation? c) What are the rise and fall times of this circuit if the parasitic capacitance at the output is 9fF? d) If a load capacitance, C_L = 25fF is added to the output, what are the new rise and fall times? e) What are the propagation delays for this circuit considering both parasitic and load capacitances?

          A CMOS inverter with minimum sized transistors has k_n =0.2mA/V^2, k_p = 0.1mA/V^2 and V_{tn}=|V_{tp}|=0.6V. Assume V_{DD} = 3.3V. a) What is the inverter gate switching threshold voltage V_{th}? b) What is the resistance for each transistors using our general expression for MOSFET resistance in saturation? c) What are the rise and fall times of this circuit if the parasitic capacitance at the output is 9fF? d) If a load capacitance, C_L = 25fF is added to the output, what are the new rise and fall times? e) What are the propagation delays for this circuit considering both parasitic and load capacitances?

A CMOS inverter with minimum sized transistors has kn =0.2mA/V^2, kp = 0.1mA/V^2 and Vtn=|Vtp|=0.6V. Assume VDD = 3.3V. a) What is the inverter gate switching threshold voltage Vth? b) What is the resistance for each transistors using our general expression for MOSFET resistance in saturation? c) What are the rise and fall times of this circuit if the parasitic capacitance at the output is 9fF? d) If a load capacitance, CL = 25fF is added to the output, what are the new rise and fall times? e) What are the propagation delays for this circuit considering both parasitic and load capacitances?

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