A quad-core i7 has an 8MB L3 cache that is 8-way set associative with a block size of 32 bytes. It uses a 30-bit block address (36-bit physical address, 6-bit block offset). What is the addressing organization of L3? Answer: Block Address= Block Offset= Index= Tag=
Added by Tiffany R.
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Since the address is byte addressable, we need 5 bits to address each byte in a block (since 2^5 = 32). Show more…
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