Question

A Von Neumann processor is defined by the following eight operations with the indicated opcodes, where both data and instructions are stored in a 4096-location memory, MEM in which each location holds 16 bits. Any location in MEM can be accessed either by loading a 12-bit address into a Memory Address Register (MAR) or using the right most 12 bits of a 16-bit Instruction Register (IR) and reading or writing a 16-bit operand or instruction in and out of MEM using a Memory Data Register (MDR), and two control signals, denoted by read and write. The address of the next instruction to be executed is found in the PC (Program Counter). The processor has a 16-bit accumulator (X) and a 16-bit co-accumulator (Y). Op-code Operation 000 MEM[ IR[4:16]] = MEM[IR[4:16] + 1] 001 MEM[ IR[4:16]] = MEM[MEM[ IR[4:16] + 1]] 010 PC = IR[4:16] 011 If (X = 0) PC = IR[4:16] 100 If (X < 0) PC = IR[4:16] 101 X << 1 110 X = ~X 111 X = X + Y (a) (15 points.) Describe the fetch-decode-execute cycle of this processor, using D-Flip Flops and other logic elements as needed and by clearly specifying the logic that drives the D and clock inputs of each flip-flop and what its Q output represents. Your solution should use as few clock cycles as possible. (b) (10 points.) Give a logic diagram to describe the behavior of a typical D-Flip-Flop in the X register, by specifying a precise logic circuit for its D and clock inputs.

          A Von Neumann processor is defined by the following eight operations with the indicated
opcodes, where both data and instructions are stored in a 4096-location memory, MEM in which
each location holds 16 bits. Any location in MEM can be accessed either by loading a 12-bit
address into a Memory Address Register (MAR) or using the right most 12 bits of a 16-bit
Instruction Register (IR) and reading or writing a 16-bit operand or instruction in and out of
MEM using a Memory Data Register (MDR), and two control signals, denoted by read and write.
The address of the next instruction to be executed is found in the PC (Program Counter). The
processor has a 16-bit accumulator (X) and a 16-bit co-accumulator (Y).
Op-code	Operation
000	MEM[ IR[4:16]] = MEM[IR[4:16] + 1]
001	MEM[ IR[4:16]] = MEM[MEM[ IR[4:16] + 1]]
010	PC = IR[4:16]
011	If (X = 0) PC = IR[4:16]
100	If (X < 0) PC = IR[4:16]
101	X << 1
110	X = ~X
111	X = X + Y
(a) (15 points.) Describe the fetch-decode-execute cycle of this processor, using D-Flip Flops
and other logic elements as needed and by clearly specifying the logic that drives the D
and clock inputs of each flip-flop and what its Q output represents. Your solution should
use as few clock cycles as possible.
(b) (10 points.) Give a logic diagram to describe the behavior of a typical D-Flip-Flop in the
X register, by specifying a precise logic circuit for its D and clock inputs.

A Von Neumann processor is defined by the following eight operations with the indicated
opcodes, where both data and instructions are stored in a 4096-location memory, MEM in which
each location holds 16 bits. Any location in MEM can be accessed either by loading a 12-bit
address into a Memory Address Register (MAR) or using the right most 12 bits of a 16-bit
Instruction Register (IR) and reading or writing a 16-bit operand or instruction in and out of
MEM using a Memory Data Register (MDR), and two control signals, denoted by read and write.
The address of the next instruction to be executed is found in the PC (Program Counter). The
processor has a 16-bit accumulator (X) and a 16-bit co-accumulator (Y).
Op-code Operation
000 MEM[ IR[4:16]] = MEM[IR[4:16] + 1]
001 MEM[ IR[4:16]] = MEM[MEM[ IR[4:16] + 1]]
010 PC = IR[4:16]
011 If (X = 0) PC = IR[4:16]
100 If (X < 0) PC = IR[4:16]
101 X << 1
110 X = X
111 X = X + Y
(a) (15 points.) Describe the fetch-decode-execute cycle of this processor, using D-Flip Flops
and other logic elements as needed and by clearly specifying the logic that drives the D
and clock inputs of each flip-flop and what its Q output represents. Your solution should
use as few clock cycles as possible.
(b) (10 points.) Give a logic diagram to describe the behavior of a typical D-Flip-Flop in the
X register, by specifying a precise logic circuit for its D and clock inputs.

Added by Lisa M.

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