Question

A. Design of a Digital Counter 1. Design a decade up counter based on the synchronous 4 bit binary counter (SN74LS161AN). Draw the state diagram of this counter and present it in the space below. 2. Complete the "present and next state table" for this counter using the following table; add or delate rows if necessary. D Current State C Next State B A D C B A 3. Derive the logic expression to reset this counter to state 0 so that it is a decade counter. For full mark, explain your reasoning to arrive at this expression. 4. Verify the counter operation using Multisim and present the schematic diagram of the simulation in the space below. Hint: using Logic Analyser to display waveforms 5. Capture the counter simulation timing diagram using the built-in logic analyser and present it in the space below. For full mark, please show the complete counting cycle. Hint: capture and show at least one and a half counting cycle. IF

          A. Design of a Digital Counter
1. Design a decade up counter based on the synchronous 4 bit binary counter
(SN74LS161AN). Draw the state diagram of this counter and present it in the space below.
2. Complete the "present and next state table" for this counter using the following table; add
or delate rows if necessary.
D
Current State
C
Next State
B
A
D
C
B
A
3. Derive the logic expression to reset this counter to state 0 so that it is a decade counter.
For full mark, explain your reasoning to arrive at this expression.
4. Verify the counter operation using Multisim and present the schematic diagram of the
simulation in the space below. Hint: using Logic Analyser to display waveforms
5. Capture the counter simulation timing diagram using the built-in logic analyser and
present it in the space below. For full mark, please show the complete counting cycle.
Hint: capture and show at least one and a half counting cycle.
IF

A. Design of a Digital Counter
1. Design a decade up counter based on the synchronous 4 bit binary counter
(SN74LS161AN). Draw the state diagram of this counter and present it in the space below.
2. Complete the "present and next state table" for this counter using the following table; add
or delate rows if necessary.
D
Current State
C
Next State
B
A
D
C
B
A
3. Derive the logic expression to reset this counter to state 0 so that it is a decade counter.
For full mark, explain your reasoning to arrive at this expression.
4. Verify the counter operation using Multisim and present the schematic diagram of the
simulation in the space below. Hint: using Logic Analyser to display waveforms
5. Capture the counter simulation timing diagram using the built-in logic analyser and
present it in the space below. For full mark, please show the complete counting cycle.
Hint: capture and show at least one and a half counting cycle.
IF

Added by Brittany B.

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