Question

8) [BB] (10 pts.) Design a circuit that takes in four 4-bit unsigned numbers, A (A3..A0), B (B3..B0), C (C3..C0), and D (D3..D0) and produces the 6-bit unsigned sum of those numbers. You should use three 4-bit adder blocks (74LS283's), and a minimal number of full adders or half adder build blocks. You should organize your adder circuits to perform as many additions in parallel (at the same time) as possible. Getting started: Write out the columns of addition and see where you can apply 4-bit adders. Use half and full adders for remaining addition operations. Block Diagram of Desired Operation: A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0 Desired Circuit (S = A[3:0] + B[3:0] + C[3:0] + D[3:0]) S5 S4 S3 S2 S1 S0 a. Which of the two initial set of connections will yield the smallest delay to produce the lower 4-bits of sum (S[3:0]). b. Indicate what should be connected to the carry-in inputs of the 4-bit adders (CX, CY, CZ) for the option you selected. c. Assuming we prefer use of full adders when necessary (rather than using multiple half-adders to mimic a full adder), how many full and half adders would you need?

          8) [BB] (10 pts.) Design a circuit that takes in four 4-bit unsigned numbers, A (A3..A0), B (B3..B0), C (C3..C0), and D (D3..D0) and produces the 6-bit unsigned sum of those numbers. You should use three 4-bit adder blocks (74LS283's), and a minimal number of full adders or half adder build blocks. You should organize your adder circuits to perform as many additions in parallel (at the same time) as possible. Getting started: Write out the columns of addition and see where you can apply 4-bit adders. Use half and full adders for remaining addition operations.

Block Diagram of Desired Operation:
A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0
Desired Circuit (S = A[3:0] + B[3:0] + C[3:0] + D[3:0])
S5 S4 S3 S2 S1 S0

a. Which of the two initial set of connections will yield the smallest delay to produce the lower 4-bits of sum (S[3:0]).
b. Indicate what should be connected to the carry-in inputs of the 4-bit adders (CX, CY, CZ) for the option you selected.
c. Assuming we prefer use of full adders when necessary (rather than using multiple half-adders to mimic a full adder), how many full and half adders would you need?

8) [BB] (10 pts.) Design a circuit that takes in four 4-bit unsigned numbers, A (A3..A0), B (B3..B0), C (C3..C0), and D (D3..D0) and produces the 6-bit unsigned sum of those numbers. You should use three 4-bit adder blocks (74LS283's), and a minimal number of full adders or half adder build blocks. You should organize your adder circuits to perform as many additions in parallel (at the same time) as possible. Getting started: Write out the columns of addition and see where you can apply 4-bit adders. Use half and full adders for remaining addition operations.

Block Diagram of Desired Operation:
A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0
Desired Circuit (S = A[3:0] + B[3:0] + C[3:0] + D[3:0])
S5 S4 S3 S2 S1 S0

a. Which of the two initial set of connections will yield the smallest delay to produce the lower 4-bits of sum (S[3:0]).
b. Indicate what should be connected to the carry-in inputs of the 4-bit adders (CX, CY, CZ) for the option you selected.
c. Assuming we prefer use of full adders when necessary (rather than using multiple half-adders to mimic a full adder), how many full and half adders would you need?

Added by Clara C.

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