b) Use Shannon's expansion theorem to design a CMOS solution to the logic function and sketch its implementation upon the CMOS Double Rail MPGA logic cell shown in figure Q4a. (8 marks)
c) Figure Q4b shows the transistor layout of a CMOS DPL cell.
i) Show how the cell in figure Q4a could be modified to physically implement it and label the connection areas shown. Commonly, CMOS cells are constructed with Xi=Xz and X=X4. Why? (5 marks)
ii) (2 marks)
Vao
Figure Q4a: CMOS Double Rail MPGA logic cell
Zi
Z
Za
Z4
X
Figure Q4b: CMOS DPL Cell Structure
