Instruction Fetch Instr. Decode Reg. Fetch Execute Addr....

Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC Adder Next SEQ PC Next SEQ PC RS1 RS2 Reg File ZERO? MUX MUX MUX1 MUX3 IF / ID ID / EX ALU EX / MEM Memory MEM / WB MUX4 Address Memory Sign Extend Imm MUX MUX MUX2 WB Data

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CPU Datapath: The following figure shows the overall datapath of the simple 5-stage CPU: There are four multiplexers (MUX) in the figure, which are labeled and numbered. Please answer the following questions regarding these multiplexers. 1. Please give the two inputs of each multiplexer. (a) MUX1: i. input 1: ii. input 2: (b) MUX2: i. input 1: ii. input 2: (c) MUX3: i. input 1: ii. input 2: (d) MUX4: i. input 1: ii. input 2: 2. Given a memory load instruction, mov R0; [R1+1000]," please give the input that should be selected at each multiplexer. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 3. Given a memory store instruction, mov [R1+1000]; R0," please give the input that should be selected at each multiplexer. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 4. Given a bitwise XOR instruction, xor R0; R1; R2," please give the input that should be selected at each multiplexer. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 5. Given a conditional branch instruction, jnz 100," please give the input that should be selected at each multiplexer. Assume the branch is not taken. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4: 6. Given an unconditional branch instruction, jmp 100," please give the input that should be selected at each multiplexer. Unconditional branches are always taken. You can write one" for the multiplexers that are not used for this instruction. (a) MUX1: (b) MUX2: (c) MUX3: (d) MUX4:

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Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC Adder Next SEQ PC Next SEQ PC RS1 RS2 Reg File ZERO? MUX MUX MUX1 MUX3 IF / ID ID / EX ALU EX / MEM Memory MEM / WB MUX4 Address Memory Sign Extend Imm MUX MUX MUX2 WB Data

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