Design a parallel differentiator. The differentiator finds the difference between adjacent samples. (You can use the example code given below as a starting point). Create a test bench to test the functionality of the differentiator. In the simulation, use the signed decimal format to be able to verify whether the differentiator can correctly report negative differences as well positive ones or not. Show and explain your verilog code for the differentiator, the test bench, and simulation results.
Example code:
module differentiator # (parameter word_size = 8) (
output [word_size -1: 0] data_out,
input [word_size -1: 0] data_in,
input hold,
input clock, reset );
reg [word_size -1:0] buffer;
assign data_out = data_in – buffer;
always @ (posedge clock) begin
if (reset) buffer <= 0;
else if (hold) buffer <= buffer;
else buffer <= data_in;
end
endmodule