Design a synchronous counter that goes through the following sequence using D flip flops: 0, 1, 3, 4, 7, and repeat.
Show/draw the following components of your design:
1. State definition table (States, Definition, Binary assignments). (8 pt)
2. State transition diagram. (8 pt)
3. State transition table. (8 pt)
4. Karnaugh Maps and corresponding equations (find the minimum SoP expressions) for an implementation using D flip-flops. (8 pt)
5. Final circuit schematic using positive edge triggered D-flip flops. (8 pt)