Design a system that can invert one single bit in a 4-bit input data, given its index. The index is a 2-bit value that specifies which bit to invert in the 4-bit input.
a) (3 pt.) Draw a hierarchical design of the circuit using any kind of combinational logic blocks presented in class. For each reused logic block, specify its exact name and size, and label its complete interface. Label the interface of the design circuit, too, matching the inputs and output. The output should be the modified 4-bit value.
b) (3 pt.) Write a SystemVerilog module for the circuit design using a structural model. If your circuit uses any auxiliary combinational blocks (multiplexer, decoder, ...) you can use any other implementation model for its SystemVerilog module (behavioral: continuous assignment or procedural).
c) (3 pt.) Write a high level SystemVerilog module for the design using a behavioral procedural model.
d) (3 pt.) Write a SystemVerilog test-bench for your two circuit design modules, exploring at least four different combinations for the inputs.
e) (2 pt.) Simulate your test-bench and show the terminal output of the simulator from testing both modules