Design a VHDL RTL model of a 32-bit, synchronous register. The block diagram for the entity definition is shown in Fig. 1. The register has a synchronous enable. The register should be modeled using a single process.
32 Data In EN
32 Data Out
Reset
Figure 1: 32-Bit Register block diagram
Note: The solution should be submitted via Moodle as a Word or a PDF file and take a Print Screen for your code and result that shows every step during working with Quartus and ModelSim programs.