Question

1. Develop an algorithm for performing 8-bit floating-point addition. 2. Draw an FSMD depicting your algorithm (see Figure 10.1 for an example). 3. Draw a data path for implementing your FSMD. 4. Draw the state diagram, along with the control/status signals, for your controller. 5. Develop Verilog code for your FSM + Data path design. 6. Simulate and verify your design with a minimum of 4 different test cases.

          1. Develop an algorithm for performing 8-bit floating-point addition.
2. Draw an FSMD depicting your algorithm (see Figure 10.1 for an example).
3. Draw a data path for implementing your FSMD.
4. Draw the state diagram, along with the control/status signals, for your controller.
5. Develop Verilog code for your FSM + Data path design.
6. Simulate and verify your design with a minimum of 4 different test cases.

1. Develop an algorithm for performing 8-bit floating-point addition.
2. Draw an FSMD depicting your algorithm (see Figure 10.1 for an example).
3. Draw a data path for implementing your FSMD.
4. Draw the state diagram, along with the control/status signals, for your controller.
5. Develop Verilog code for your FSM + Data path design.
6. Simulate and verify your design with a minimum of 4 different test cases.

Added by Patricia H.

Computer Science and Information Technology

Trishna Knowledge Systems 2018 Edition

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Solved by Expert James Kiss

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Algorithm for performing 8-bit floating-point addition: Step 1: Convert the two 8-bit floating-point numbers into their binary representation. Step 2: Determine the exponent and mantissa for each number. Step 3: Align the exponents by shifting the mantissa of the Show more…

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Develop an algorithm for performing 8-bit floating-point addition. 2. Draw an FSMD depicting your algorithm (see Figure 10.1 for an example) 3. Draw a data path for implementing your FSMD. 4. Draw the state diagram, along with the control/status signals, for your controller 5. Develop Verilog code for your FSM + Data path design. 6. Simulate and verify your design with a minimum of 4 different test cases.