Question

1. Draw the logic circuits based on the following Verilog codes 1) always @* begin y = a; y = y | b; y = y & c; end 2) always @ (posedge clk) begin y = a | b; q0 <= y; end 2. module eq (input wire a, b, output reg eq); always @* #20 eq = ((~a&~b)|(a&b)); endmodule 1) Convert to the Verilog code with Task statements. 2) Convert to the Verilog code with Function statements

          1. Draw the logic circuits based on the following Verilog codes
1) always @*
begin
y = a;
y = y | b;
y = y & c;
end
2) always @ (posedge clk)
begin
y = a | b;
q0 <= y;
end
2. module eq
(input wire a, b,
output reg eq);
always @*
#20 eq = ((~a&~b)|(a&b));
endmodule
1) Convert to the Verilog code with Task statements.
2) Convert to the Verilog code with Function statements

1. Draw the logic circuits based on the following Verilog codes
1) always @*
begin
y = a;
y = y | b;
y = y c;
end
2) always @ (posedge clk)
begin
y = a | b;
q0 <= y;
end
2. module eq
(input wire a, b,
output reg eq);
always @*
#20 eq = (( a b)|(a b));
endmodule
1) Convert to the Verilog code with Task statements.
2) Convert to the Verilog code with Function statements

Added by Jeremy J.

Computer Science and Information Technology

Trishna Knowledge Systems 2018 Edition

Instant Answer

Solved by Expert John Incabo

Step 1

In this case, we can define a task for each of the given Verilog codes. For the first Verilog code: ``` task logic_circuit_1; input wire a, b, c; output wire y; begin y = a; y = y | b; y = y & c; end endtask ``` For the second Verilog Show more…

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Digital System Design 1. Draw the logic circuits based on the following Verilog codes: 1) always @ begin y = a; y = y | b; y = y & c; end 2) always @(posedge clk) begin y = a | b; q0 <= y; end 2. module eq (input wire a, b, output reg eq): always @* #20 eq = (~a & ~bla & b); endmodule 1) Convert to the Verilog code with Task statements 2) Convert to the Verilog code with Function statements