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Exercise 3. Parallelism, Latency, and Throughput: Consider the circuit below. Suppose the delay of each gate is 10-30ps and the flip-flop timing characteristics are as shown Table 1. Table 1. Flip-flop timing characteristics Characteristic Value (in ps) tpcq 50 tccq 40 tsetup 100 thold 30 a) What is the highest frequency at which this circuit will run reliably? b) How much clock skew can the circuit tolerate? c) Add registers to parallelize (also called pipeline) the circuit so that throughput is maximized. d) With the added registers, what is the new clock frequency at which the circuit will run reliably? e) With the added registers, what is the throughput? f) With the added registers, what is the latency? g) With the added registers, how much clock skew can the circuit tolerate?

          Exercise 3. Parallelism, Latency, and Throughput: Consider the circuit below. Suppose the delay of each gate is 10-30ps and the flip-flop timing characteristics are as shown Table 1.
Table 1. Flip-flop timing characteristics
Characteristic	Value (in ps)
tpcq	50
tccq	40
tsetup	100
thold	30
a) What is the highest frequency at which this circuit will run reliably?
b) How much clock skew can the circuit tolerate?
c) Add registers to parallelize (also called pipeline) the circuit so that throughput is maximized.
d) With the added registers, what is the new clock frequency at which the circuit will run reliably?
e) With the added registers, what is the throughput?
f) With the added registers, what is the latency?
g) With the added registers, how much clock skew can the circuit tolerate?

exercise 3 parallelism latency and throughput consider the circuit below suppose the delay of each gate is 10 30ps and the flip flop timing characteristics are as shown table 1 table 1 flip 77602

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