For items 11 to 25 , a finite state machine acting on a clock signal C 's rising edge has an active-low asynchronous reset signal R. It has two inputs A and B, and an output Y. Its state diagram is shown below, where the initial state is Q_(1)Q_(0)=00 with Y=0.
11. to 15. Use D flip-flops to represent the state variables Q_(1),Q_(0). Create the state table.
16. to 20. Use Karnaugh maps to find expressions of D_(1) and D_(0) as minimum sums of products.
21. to 25 . Draw the logic circuit.
with Y=0.
A=1 11/1 01/1
A=0 B=1
A=0
10/0 00/0 A=1
start
state table.
sums of products. 21. to 25.Draw the logic circuit.