Simulation Project 2: Influence of the Cache Size in Multiprocessor
Purpose:
Study the influence of the cache size on the miss rate during the execution of a parallel program in a SMP (symmetric multiprocessor).
Development:
Configure a system with the following architectural characteristics:
Processors in SMP = 8.
Cache coherence protocol = MESI.
Scheme for bus arbitration = LRU.
Word wide (bits) = 16.
Words by block = 32 (block size = 64 bytes).
Blocks in main memory = 524288 (main memory size = 32 MB).
Mapping = Set-Associative.
Cache sets = They will vary depending on the number of blocks in cache, but you must always have four-way set associative caches (remember: Number_of_ways = Number_of_blocks_in_cache / Number_of_cache_sets).
Replacement policy = LRU.
Configure the blocks in cache using the following configurations: 16 (cache size = 1 KB), 32, 64, 128, 256, 512, 1024, and 2048 (cache size = 128 KB). For each of the configurations, obtain the global miss rate for the system using the trace files: FFT.
Discussion:
Does the global miss rate increase or decrease as the cache size increases? Why? Does this increment or decrement happen for all the trace files? What does it happen with the capacity and conflict (collision) misses when you enlarge the caches? And, what does it happen with the compulsory and coherence misses when you enlarge the caches? Are there conflict misses in these experiments? Why?
In these experiments, it may be observed that for great cache sizes, the miss rate is stabilized. Why? We can also see great differences of miss rate for a concrete increment of cache size. What do these great differences indicate? Do these great differences of miss rate appear at the same point for all the programs? Why?
In conclusion, does the increase of cache size improve the multiprocessor system performance?