P1 (10 points). Consider a 2-to-1 multiplexer:
a. Draw the gate level implementation using only 2 AND gates, 1 OR gate, and 1 NOT gate.
b. Write the POS expression for the multiplexer.
P2 (15 points). Using the specified circuit element(s), implement the following:
a. One 3-input OR gate using only two 2-to-1 multiplexers.
b. One 2-input OR gate using only four 1-to-2 decoders (hint: Use the enable bit).
c. One 2-input NOR gate using only one 2-to-4 decoder.
P3 (10 points). Answer the following questions about decoders and MUXes:
a. How many 2-to-4 decoders are necessary to create a 4-to-16 decoder?
b. How many 3-to-8 decoders are necessary to create a 6-to-64 decoder?
c. How many 1-bit 2-to-1 MUXes are necessary to create a 1-bit 8-to-1 MUX?
d. How many 1-bit 2-to-1 MUXes are necessary to create an 8-bit 2-to-1 MUX?
P4 (20 points). Logic block G represents a 4-input logic circuit with 3 outputs controlling a decoder. Design G, such that the outputs match the truth table shown. Assume the decoder is active high and Out is always enabled.
U 0 0 Y7 0 Y5 0 +X Y3 A 2 0 0 Y2 B 1 0 0 G c 0 Y3 Y2
0
T0 IX Y7 T4 Y7 Y6
3-to-8 Decoder
a. Write the simplified logic expression for output A.
b. Write the simplified logic expression for output B.
c. Write the simplified logic expression for output C.
