Question

Add 4 PC Add Sum Shift left 1 Branch MemRead MemtoReg Instruction [6-0] Control ALUOP MemWrite ALUSrc RegWrite Instruction [19-15] Read register 1 Read Instruction [24-20] data 1 Read register 2 Instruction [11-7] Write Read register data 2 Write Read address Instruction [31-0] Instruction memory Mux Mux Zero ALU ALU result Address Read data MUXO data Registers Data Write data memory Instruction [31-0] 32 64 Imm Gen ALU control Instruction (30,14-12) Figure 1: A RISC V Processor Datapath 5. Given the Following RISCV pipeline stage latencies and the instruction mix (Fig 2) in a given benchmark, what is the utilization of the Address input port of Data memory? ALU/Logic Jump/Branch Load Store IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps 45% 20% 20% 15%

          Add
4
PC
Add Sum
Shift
left 1
Branch
MemRead
MemtoReg
Instruction [6-0]
Control
ALUOP
MemWrite
ALUSrc
RegWrite
Instruction [19-15]
Read
register 1 Read
Instruction [24-20]
data 1
Read
register 2
Instruction [11-7]
Write
Read
register
data 2
Write
Read
address
Instruction
[31-0]
Instruction
memory
Mux
Mux
Zero
ALU ALU
result
Address Read
data
MUXO
data Registers
Data
Write
data memory
Instruction [31-0]
32
64
Imm
Gen
ALU
control
Instruction (30,14-12)
Figure 1: A RISC V Processor Datapath
5. Given the Following RISCV pipeline stage latencies and the instruction mix (Fig 2) in a given benchmark, what is the
utilization of the Address input port of Data memory?
ALU/Logic Jump/Branch Load Store
IF
ID
EX MEM WB
250 ps 350 ps 150 ps 300 ps 200 ps
45%
20%
20% 15%

Add
4
PC
Add Sum
Shift
left 1
Branch
MemRead
MemtoReg
Instruction [6-0]
Control
ALUOP
MemWrite
ALUSrc
RegWrite
Instruction [19-15]
Read
register 1 Read
Instruction [24-20]
data 1
Read
register 2
Instruction [11-7]
Write
Read
register
data 2
Write
Read
address
Instruction
[31-0]
Instruction
memory
Mux
Mux
Zero
ALU ALU
result
Address Read
data
MUXO
data Registers
Data
Write
data memory
Instruction [31-0]
32
64
Imm
Gen
ALU
control
Instruction (30,14-12)
Figure 1: A RISC V Processor Datapath
5. Given the Following RISCV pipeline stage latencies and the instruction mix (Fig 2) in a given benchmark, what is the
utilization of the Address input port of Data memory?
ALU/Logic Jump/Branch Load Store
IF
ID
EX MEM WB
250 ps 350 ps 150 ps 300 ps 200 ps
45%
20%
20% 15%

Added by Jeffrey C.

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