Identify the critical path and short path of the logic shown on the right. Determine the propagation delay and contamination delay of the logic. Finally, complete the timing diagram for the given logic.
Assume that the propagation delays of the inverter, OR gate, NAND gate and NOR gate are 1ns,3ns,4ns, and 5ns, respectively.
Identify the critical path and short path of
the logic shown on the right.Determine
the propagation delay and contamination
delay of the logic.Finally.complete the
timing diagram for the given logic.
Assume that the propagation delays of the inverter, OR gate, NAND gate and NOR gate
are 1 ns.3 ns.4 ns.and 5 ns.respectively
B
c
Y
Z
0 ns
1 ns
2 ns 3 ns
4 ns
5 ns
6 ns 7 ns
8 ns 9ns 10 ns 11ns 12ns 13ns 14 ns 15 ns 16 ns