In a single-cycle datapath design of the RISC-V architecture, which of the following descriptions are correct? (20%)
(a) The data flow of R-type instruction does not go through the data mem.
(b) The data flow of SW goes through all components in a clock cycle.
(c) The data flow of LW goes through all components at most once in a clock cycle.
(d) The data flow of J-type instruction goes through all components. (answer is a, b)