Consider the following sequence of instructions:
ins1: lw x4, 0(x2)
ins2: add x4, x4, x3
ins3: sw x4, 0(x2)
ins4: addi x2, x2, 0x4
ins5: lw x5, 0(x2)
ins6: add x4, x4, x5
ins7: addi x2, x2, 0x4
ins8: sw x4, 0(x2)
Assume 5-stage RISC-V pipeline (assuming there is forwarding). Show how the instructions given above make progress in the pipeline and show the pipeline stalls that would occur. Also indicate the places where the forwarding happens.How many cycles does it take to execute the given instructions?
You can use similar table representation as given below for the pipeline to simplify the depiction. For this illustration, assume that there is a dependency between Instruction1 and Instruction2 which can be handled by forwarding from EX/MEM pipeline register to ID/EX pipeline register. On the other, assume there is load-use case between Instruction2 and Instruction3, so the dependence could not be handled by just forwarding, so it was stalled by one cycle (this is for just illustration purpose, in your solution you should provide similar details for the given instruction sequence above).
Instruction | Cycle 1 | Cycle 2 | Cycle 3 | Cycle 4 | Cycle 5 | Cycle 6 | Cycle 7 | Cycle 8
Instruction1 | IF | ID | EX | MEM | WB | | |
Instruction2 | | IF | ID | EX (forwarding from EX/MEM to ID/EX for Instruction1 and Instruction 2) | MEM | WB | |
Instruction3 | | | IF | Stall (load-use case for Instruction2 and Instruction3) | ID (forwarding from MEM/WB to ID/EX for Instruction2 and Instruction3) | EX | MEM | WB