Question

Delay optimization and implementation of a logic path The figure below shows a 3-stage logic path. For all the transistors, L = 30nm and VDD = 1.05V. The input signal is a linear ramp input with Tr = Tf = 30ps (between 0% and 100% VDD). The load capacitance at the final output node is an inverter which is 25.64 times the size of the first inverter. Note: This final inverter is the load when you do the simulation. It is NOT included in the layout. In Out Tr WN1 = 420 nm WN2 = X nm WN3 = Y nm WN4 = 10772 nm a. All four gates are implemented with complementary static logic, with PUN and PDN having the same drive capability (i.e., PMOS and NMOS are appropriately sized) - please appropriately size the ratio of PMOS/NMOS first. Describe your ratio of the transistors in the report. b. Use logical efforts to estimate the size WN2 and WN3, such that the delay from In to Out is minimized. Please include your hand calculation in the report. c. Create the HSPICE testbench to simulate the schematic from In to Out, and monitor the delay. What's the value of tpHL and tpLH from In to Out?

          Delay optimization and implementation of a logic path

The figure below shows a 3-stage logic path. For all the transistors, L = 30nm and VDD = 1.05V. The input signal is a linear ramp input with Tr = Tf = 30ps (between 0% and 100% VDD). The load capacitance at the final output node is an inverter which is 25.64 times the size of the first inverter.
Note: This final inverter is the load when you do the simulation. It is NOT included in the layout.

In Out
Tr
WN1 = 420 nm WN2 = X nm WN3 = Y nm WN4 = 10772 nm

a. All four gates are implemented with complementary static logic, with PUN and PDN having the same drive capability (i.e., PMOS and NMOS are appropriately sized) - please appropriately size the ratio of PMOS/NMOS first. Describe your ratio of the transistors in the report.

b. Use logical efforts to estimate the size WN2 and WN3, such that the delay from In to Out is minimized. Please include your hand calculation in the report.

c. Create the HSPICE testbench to simulate the schematic from In to Out, and monitor the delay. What's the value of tpHL and tpLH from In to Out?

Delay optimization and implementation of a logic path

The figure below shows a 3-stage logic path. For all the transistors, L = 30nm and VDD = 1.05V. The input signal is a linear ramp input with Tr = Tf = 30ps (between 0% and 100% VDD). The load capacitance at the final output node is an inverter which is 25.64 times the size of the first inverter.
Note: This final inverter is the load when you do the simulation. It is NOT included in the layout.

In Out
Tr
WN1 = 420 nm WN2 = X nm WN3 = Y nm WN4 = 10772 nm

a. All four gates are implemented with complementary static logic, with PUN and PDN having the same drive capability (i.e., PMOS and NMOS are appropriately sized) - please appropriately size the ratio of PMOS/NMOS first. Describe your ratio of the transistors in the report.

b. Use logical efforts to estimate the size WN2 and WN3, such that the delay from In to Out is minimized. Please include your hand calculation in the report.

c. Create the HSPICE testbench to simulate the schematic from In to Out, and monitor the delay. What's the value of tpHL and tpLH from In to Out?

Added by Melissa L.

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