Please don't solve one question. I want the first question with parts A to G and the second question.
A. Draw a Block Diagram for your design and label inputs and outputs.
X1 XOR Y1 = OGE
B. Generate the equation for LT using a Minimize SOP. Use only NAND gates.
C. Clearly label.
G. Implement the circuits for GT and LT using a 74138 3-to-8 decoder-based approach. Make sure all signals are clearly labeled.
Question 8. Label all connections and circuitry clearly.