Please help me solve this.
Consider the below multiplexer SystemVerilog module:
module what(input logic W, X, Y, Z, output logic F);
logic [15:0] MAP;
assign MAP = 16'b0000000000000000; // This value should be replaced
assign F = MAP[{W, X, Y, Z}];
endmodule
What value should you use instead of 16'b0000000000000000 so that the module implements the following Boolean function:
F(W, X, Y, Z) = YZ + XY'Z' + W'X'YZ
1. 16'b0011_0010_0011_0110
2. 16'b1001_1000_1001_1100
3. 16'b1010_1010_0001_0100
4. 16'b0111_0001_0101_0001
5. None of the others