Please help PMOS logic NOR gate pull down.
Please answer at least (b) and (c).
(a) Define propagation time tpH for falling logic transitions, making clear how it differs from fall time.
(b) A PMOS logic NOR gate uses a passive pull-down resistor of value 10k and drives a load capacitance of 8pF. Estimate the propagation time tpHL.
(c) A single NPN bipolar junction transistor with a passive pull-up is used as a logic inverter driving a +5.0V. The input voltage is applied to one end of a 47k resistor; the other end of the resistor is the base-emitter junction that has a turn-on voltage Von = 0.7V. Estimate the propagation time tpHL.