5.2.3 4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset: Write a Verilog code to read an 8-bit message from parallel input (user switches) into a shift-register, and use the shift function together with a counter to determine the number of '1's in the message (Don't use behavioral design instead use d flip-flops). (no need for designing the 7-segment LED decoder here, the decoder will be used during the experimental work.) 5.2.4 Testbench for 4-Bit Synchronous Parallel Load Shift Register with Counter and Asynchronous Reset: To test your design, write a testbench using the template given in lab4 and use the following test patterns with the clock periods provided. Use ModelSim® simulator and demonstrate the functionality of your design to the lab instructor before proceeding.
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A D flip-flop is a type of flip-flop that takes an input and gives an output that is the same as the input at the next clock cycle. Here is a simple Verilog code for a 4-bit shift register: ```verilog module shift_register ( input wire clk, input wire Show more…
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Design a 4-bit shift register with the following specifications: - An asynchronous active-low clear (ClrN) - A rising-edge triggered clock (CLK) - An active-high load signal (Ld) with parallel data input (D) - A function select signal (S) - When S = 0, the register shifts right with a serial data input (SI) - When S = 1, the register shifts right with sign extension (copy the sign bit) a) Draw the logic symbol and a truth table for the 4-bit shift register. b) Write a complete VHDL model (entity and behavioral architecture) for the 4-bit shift register. c) Write a VHDL testbench for the 4-bit shift register. Simulate the shift register for the following test sequence: - Load 0011 - Shift right 3 times with S = 0 and SI = 1 - Shift right 2 times with S = 0 and SI = 0 - Clear - Load 1100 - Shift right 2 times with S = 1 and SI = 0
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