Problem 3: Design a MOS ROM 4 words x 4 bits circuit where the five words stored are: (W1) 1110, (W2) 0101, (W3) 0110 & (W4) 1001. In the schematic, you must identify: the row decoder (how many inputs does it need), the PMOS transistors (NB: let the gate of all PMOSs be connected to a precharge control signal), the NMOS transistors, and the bit lines.
Let all the NMOS devices have W/L = 3 and all the PMOS devices have W/L = 12. Assume that nCox = 50 uA/V^2, uCox = 20 uA/V^2, Vm = -V = 1 V, and Vpp = 5 V.
a- During the precharge interval, Vpd is lowered to 0 V. Calculate the rise time required to charge a bit line from 10% to 90% of Vpd. Use the average charging current method (the current supplied by a PMOS). The bit-line capacitance is 2 pF. Note that all NMOS transistors are cut off at this time.
b- After completion of the precharge interval and the return of Vpd to Vpd, the row decoder raises the voltage of the selected word line. Find the interval At required for an NMOS transistor to discharge the bit line and lower its voltage by 0.5 V.