Procedure D: Half adder circuit using NAND gates Half Adder 74XX00 Chip 1 Pin 7: GND Pin 14: 5V DC NAND1 NAND2 NAND3 NAND4 SUM A B 74XX00 Chip 2 Pin 7: GND Pin 14: 5V DC NAND5 CARRY Figure 7: Half adder circuit using NAND gates A B SUM CARRY 0 0 0 1 1 0 1 1 Table 4: Half adder truth table

          Procedure D:
Half adder circuit using NAND gates
Half Adder
74XX00 Chip 1
Pin 7: GND
Pin 14: 5V DC
NAND1
NAND2
NAND3
NAND4
SUM
A
B
74XX00 Chip 2
Pin 7: GND
Pin 14: 5V DC
NAND5
CARRY
Figure 7: Half adder circuit using NAND gates
A
B
SUM
CARRY
0
0
0
1
1
0
1
1
Table 4: Half adder truth table

Procedure D:
Half adder circuit using NAND gates
Half Adder
74XX00 Chip 1
Pin 7: GND
Pin 14: 5V DC
NAND1
NAND2
NAND3
NAND4
SUM
A
B
74XX00 Chip 2
Pin 7: GND
Pin 14: 5V DC
NAND5
CARRY
Figure 7: Half adder circuit using NAND gates
A
B
SUM
CARRY
0
0
0
1
1
0
1
1
Table 4: Half adder truth table

Added by Lisa A.

University Physics with Modern Physics

Hugh D. Young 14th Edition

Instant Answer

Solved by Expert Sri K

07/12/2023

Step 1

Connect pin 7 of chip 1 to GND and pin 14 of chip 2 to 5V. Show more…

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Procedure D: Half adder circuit using NAND gates Half Adder 74XX00 Chip 1 Pin 7: GND Pin 14: 5V DC NAND1 NAND2 NAND3 NAND4 SUM A B 74XX00 Chip 2 Pin 7: GND Pin 14: 5V DC NAND5 CARRY Figure 7: Half adder circuit using NAND gates A B SUM CARRY 0 0 0 1 1 0 1 1 Table 4: Half adder truth table