CLK- D Fig. 1 Given the input and clock transitions in Fig....

CLK- D Fig. 1 Given the input and clock transitions in Fig. 1 indicate the output of the D flip-flop assuming: a. It is a negative edge-triggered flip-flop. b. It is a positive edge-triggered flip-flop. c. It is a clocked latch. d. Indicate set up time, hold time and clock to Q delay in the figure.

Transcript

00:02 Hi, so we are given that a clobbed pulse for that we have to represent it as in the first part that is it is a negative edge trigger negative edge triggered flip flop.

00:23 So the diagram is see the clock is something like in this way i'm just drawing the two of them for just understanding purpose let's draw the complete one.

00:36 So in this way the d flip flop is having the output something like this way and it is so on it is high.

00:47 So as you can see this part of the clock okay this one is representing the clock this is what the d input and in the below of it we are going to take the output of d.

01:01 To see as this clock going down here also the clock going down.

01:08 So in this case we are going to get the zero right here as per the response that you can see here.

01:15 So we are just getting a down means a zero pulse right at this place.

01:22 So in this way the output pulse can be drawn like in this way and here it will be the sct at time means a schematic time.

01:34 So it's corresponding to this and here this one representing the hold time.

01:42 So this is what the output according to negative triggered flip flop.

01:47 Now if it will be something new that is it is a positive edge triggered flip flop in that case it can be drawn something like in this way let's suppose this are what the clock pulse that i'm drawing here.

02:06 I'm just drawing the rough diagram so don't be let it as a complete one and this is what input from the d flip flop.

02:17 So according to this when it's going positive edge trigger means to say when it will go towards the high.

02:27 So all of this will represent the positive edge trigger.

02:34 So corresponding to this what will be the value of it that's going to be the required output.

02:41 So basically this is the d input here it is zero here it is high and now here it is a zero.

02:52 So what will be the required output in this case.

02:55 So corresponding to this dash lines its output is going to get that is here it will be zero up to this much of the time which is going to be high then again it will be zero and high.

03:12 So this is what the output when it is positive triggered.

03:16 Now in the same way let's have a look for another c part where to give the clocked latch.

03:28 In clocked latch again we are to consider the given clock pulse according to the diagram.

03:34 I'm just drawing the rough diagram here deep input and output...

Question

CLK- D Fig. 1 Given the input and clock transitions in Fig. 1 indicate the output of the D flip-flop assuming: a. It is a negative edge-triggered flip-flop. b. It is a positive edge-triggered flip-flop. c. It is a clocked latch. d. Indicate set up time, hold time and clock to Q delay in the figure.

Please give Ace some feedback