Question 1: We wish to build a 3-bit synchronous counter using edge-triggered J-K flip-flops with outputs Q3, Q2, and Q1. A schematic diagram (minus the logic for the flip-flop inputs) is shown below:
The counter must output the following sequence of decimal numbers in 3-bit binary:
2 → 4 → 7 → 5 → 2 → ....
The output of the counter is Q3Q2Q1. Assume that the counter never starts or gets into an illegal state.
(a) Write down the state diagram for this counter.
(b) Write down the next state table for this counter.
(c) Write down the flip-flop transition table for a J-K flip-flop.
