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Question 1: A digital system-on-chip in a 1.2 V 100 nm process has 200million transistors, of which 20 million are in logic gates and the remainder in memory arrays. The average logic transistor width is 12 ? and the average memory transistor width is 4 ?. The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage is 20 nA/µm for low-threshold devices and 0.02 nA/µm for high-threshold devices. Gate leakage is 3 nA/µm for thin oxides and 0.002 nA/µm for thick oxides. Memory use low-leakage devices everywhere. Logic uses low-leakage devices in all but 20% of the paths that are most critical for performance. Diode leakage is negligible. Estimate the static power consumption. How would the power consumption change if the low- leakage devices were not available? Assume that ½ transistors have subthreshold leakage and ½ transistors have gate leakage.

          Question 1:
A digital system-on-chip in a 1.2 V 100 nm process has 200million transistors, of which 20
million are in logic gates and the remainder in memory arrays. The average logic transistor width
is 12 ? and the average memory transistor width is 4 ?. The process has two threshold voltages
and two oxide thicknesses. Subthreshold leakage is 20 nA/µm for low-threshold devices and 0.02
nA/µm for high-threshold devices. Gate leakage is 3 nA/µm for thin oxides and 0.002 nA/µm
for thick oxides. Memory use low-leakage devices everywhere. Logic uses low-leakage devices
in all but 20% of the paths that are most critical for performance. Diode leakage is negligible.
Estimate the static power consumption. How would the power consumption change if the low-
leakage devices were not available? Assume that ½ transistors have subthreshold leakage and ½
transistors have gate leakage.

Question 1:
A digital system-on-chip in a 1.2 V 100 nm process has 200million transistors, of which 20
million are in logic gates and the remainder in memory arrays. The average logic transistor width
is 12 ? and the average memory transistor width is 4 ?. The process has two threshold voltages
and two oxide thicknesses. Subthreshold leakage is 20 nA/µm for low-threshold devices and 0.02
nA/µm for high-threshold devices. Gate leakage is 3 nA/µm for thin oxides and 0.002 nA/µm
for thick oxides. Memory use low-leakage devices everywhere. Logic uses low-leakage devices
in all but 20% of the paths that are most critical for performance. Diode leakage is negligible.
Estimate the static power consumption. How would the power consumption change if the low-
leakage devices were not available? Assume that ½ transistors have subthreshold leakage and ½
transistors have gate leakage.

Added by Rachel J.

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