00:01
For this question, solution here is, here by taking dc analysis, the formula for the drain current is equal to k divided by 2 in bracket voltage drop across the source and the gate minus mod voltage in pmos transistor mod bracket complete the whole square.
00:29
So, by putting the value, here we get plus minus 1 is equal to voltage fall across the source and gate minus 1.
00:43
So voltage across the source gate is equal to 2 volt and 0 volt.
00:53
So, here the formula for the voltage fall in the source and gate is equal to voltage across source minus voltage across the gate.
01:09
So here we get the value of voltage across fall across the gate is 3 volt and if we put the value of vsg is equal to 0.
01:25
So here we get vg is 5.
01:29
It is not possible.
01:31
So here the value of voltage fall across gate is 3 volt.
01:36
Now for the saturation reason vsd is greater than vsg minus mod vtp mod...