The LC-3 LD and LDI instructions are not strictly necessary, and can be replaced by a sequence of two or more other instructions. In this problem, you will write an instruction sequence that has the same effect as the LD and LDI instructions without using those instructions. Enter your answers in hexadecimal. You may use up to 5 instructions. Fill unused instruction slots with NOP instructions (x0000). Your answer will be graded by executing the instruction sequence starting at the first address (x3000 or x3800) until the instruction at the last address (x3004 or x3804) finishes executing. Give an instruction sequence that is equivalent to an instruction LD R0, #-23 placed at address x3000 in memory. Your instruction sequence must have the same effect on contents of registers R0-R7, CC, and memory as the original LD instruction. Your solution must not execute an LD or LDI instruction. x3000: x3001: x3002: x3003: x3004: Give an instruction sequence that is equivalent to an instruction LDI R1, #13 placed at address x3800 in memory. Your instruction sequence must have the same effect on contents of registers R0-R7, CC, and memory as the original LDI instruction. Your solution must not execute an LD or LDI instruction. x3800: x3801: x3802: x3803: x3804:
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QUESTION 3 (30 marks) Consider an hypothetical processor having a 16-bit instructions composed of two fields: the first four bits contains the opcode, and the remainder the immediate operand and/or operand address. Assume that the hypothetical machine has the following instructions: 0001 = Load AC from Memory location 0011 = Load AC from I/O 0010 = Store AC to memory location 0101 = Add AC to memory location 1100 = Subtract AC from memory location 1101 = Divide AC with memory location 1110 = Store AC to I/O where AC is accumulator, and I/O is input/output. 3.1) - Write the code (in hexadecimal format) for each of the following instructions: i. Load AC from memory location 941 ii. Add content of memory location 940 iii. Divide by content of location 941 iv. Store AC to device 245. State any assumption that you make, if any. 3.2) - Use the format of Figure 1 to show program execution for the four instructions of above. • A blank chart to be used for this question can be found on the next page of this question paper. • For this question, assume that memory location 940 and 941 to contain 88 and 2 respectively. • You are required to state any assumptions associated with your answer.
Adi S.
A hypothetical ISA supports 6 different operations. How many bits of the instruction must be allocated for the opcode field? 1. The operands must also be encoded into the instruction. The most common type of operand is a value contained in a register in the processor's register file. Since the value is in a register, we just need to encode enough information to identify which register. The hypothetical ISA from the previous question states that the register file contains 32 registers. How many bits must be allocated to identify each register operand? 2. The hypothetical ISA from the previous questions on this page includes an ADD instruction that performs the operation Rd. Note that the arrow (←) used in the above notation points to where the result of the operation will be stored. When the processor executes this instruction, it will read the values from the source registers symbolized by Ra and Rb and stores their sum in the destination register symbolized by Rd. How many bits do we need to encode the ADD instruction? 3. Some instructions have different numbers of operands. The hypothetical ISA from the previous questions on this page also has a bitwise NOT instruction that performs the operation Rd, and which only requires one source register. Remember we will always assume that all instructions in a given ISA are encoded with the same number of bits. If all instructions in this ISA are as long as the ADD instruction, how many bits would be unused when encoding the NOT instruction?
Supreeta N.
'Q: Compute the physical address for the specified operand in each of the following instructions The register contents and variable are as follows: (CS)-OAOOH, (DS)-OBOOH, (SS)-ODOOH (Si)-OFFOH, (DI)=OOBOH, (BP)-OOEAH and (IP)-OOOOH, LIST-OOFOH, AX-4020H, BX-2SOOH: 1) Destination operand of the instruction MOV LIST [BP+DI] , AX 2) Source operand of the instruction MOV CL , [BX+2OOH] 3) Destination operand of the instruction MOV [Dl+6400H] , DX 4) Source operand of the instruction MOV AL, [BP+SI-4OOH] 5) Destination operand of the instruction MOV [Dl+SP] AX 6) Source operand of the instruction MOV CL , [SP+ZOOH] 7) Destination operand of the instruction MOv [BX+Dl+6400H] CX 8) Source operand of the instruction MOV AL , [BP- O2O0H] 9) Destination operand of the instruction MOv [SI] , AX 10) Destination operand of the instruction MOV [BXJ[DI]+O4OOH,AL 11) Source operand of the instruction MOV AX, [BP+ZOOH] 12) Source operand of the instruction MOV AL, [SI-O1OOH] 13) Destination operand of the instruction MOV DI; [SI] 14) Destination operand of the instruction MOV [DI]+CFOOH,AH 15) Source operand of the instruction MOV CL, LIST[BX+ZOOH]'
Sri K.
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