Translate the following procedure to RISC-V assembly:
long long int FUN1(long long int x, long long int y) {
return (x+y) + FUN2(y,x);
}
You can assume that there is a procedure FUN2. Your program has to respect the associativity and order of execution (i.e. you have to compute x+y before calling FUN2). You have to follow the conventions of procedure calling.
Then write a module that implements a half adder using the always construct of Verilog.