RANDOM MEMORY ACCESS (RAM) EMULATOR: The following circuit is a memory with 8 addresses, each address holding a 4-bit data. The memory positions are implemented by 4-bit registers. The resetn and clock signals are shared by all the registers. Data is written onto (or read from) one of the registers. Memory Write (wr_rd = 1): The 4-bit input Din is written into one register. The address [2..0] signal selects the register to be written. Here, the 7- segment display must show 0. Example: if address= "101", then Din is written into register 5. Memory Read (wr_rd = 0): The MUX output appears on the 7-segment display (hex. value). The address [2..0] signal selects the register from which data is read. For example, if address= "010", then data in register 2 appears on the 7-segment display. If data in register 2 is "1010", then the symbol 'A' appears on the 7-segment display.
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The entity will have inputs for the clock, resetn, wr_rd, Din, and address signals, and an output for the 7-segment display. ```vhdl entity RAM is Port ( clock : in STD_LOGIC; resetn : in STD_LOGIC; wr_rd : in STD_LOGIC; Din : Show more…
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