Q10 [12pt]. Given the following 3 caches, for each, find the shortest possible repeating memory access pattern that would cause the worst-case performance (all misses). Given: cache size - 8 words total. Cache line - 2 words. address bit width - 6 bits (word addressed)
For each:
(i) DRAW THE CACHE (with all labels)
(ii) DRAW THE ADDRESS STRUCTURE (with labels and number of bits)
(iii) LIST THE REPEATING MEMORY ACCESS PATTERN REQUESTED ABOVE
A. Fully Associative
B. Direct Mapped
C. 2-way Set associative.