We discussed one type of cache system, a direct-mapped cache of words (DMCW), to which cache line would the word at main memory address 0x16C map to, i.e., what is the cache index? Fill in the blank with your answer, expressed as a decimal integer.
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For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: Tag (31-12), Index (11-6), Offset (5-0). a. What is the cache block size in words? b. How many entries does this cache have? c. What is the ratio between the total bits required for such a cache implementation and the data storage bits?
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