what is the transistor count for the FSMs combinational logic clock? Assume a 2 input AND requires 6 transistors, a two input OR gate requires 6 transistors and a NOT gate requires 2 transistors A.12 B. 42 C.36 D.48
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To determine the transistor count for the FSM's combinational logic clock, we need to analyze the logic gates involved and their respective transistor requirements. Show more…
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Shown below is a FSM with 32 states. The two inputs are X and Y, in this order (that is, from state A, X=0 and Y=1 leads to state B). Note that the arrows which extend off of the sides wrap around to the top to complete the pattern (that is, from state MM, input 10 goes to state E, and input 11 goes to state F). Input 01 always goes to the state on the right, 10 to the state beneath, and 11 downwards and to the right. The five output bits are, in order from most to least significant for the output integers: z1 z0 w2 w1 w0. Answer the following questions: A: What is the minimum number of state variables that can be used to implement this FSM? B: What is the minimum number of TFFs that can be used to implement this FSM? C: How many total state transitions exist in this FSM? D: Suppose that input X were always connected to ground. Draw the new state diagram (hint: the reset state is always reachable). How many states and state transitions would be removed (note: a state transition is removed if its beginning state or its end state are removed)? E: Suppose instead that input Y were always connected to ground. Draw the new state diagram. How many states and state transitions would be removed? F: What two circuits implemented separately would implement this 32-state FSM? Why? (Hint: What FSM did the 32-state FSM reduce to in step D?)
Adi S.
Figure $P 13.56$ shows two approaches to realizing the OR function of six input variables. The circuit in Fig. $\mathrm{P} 13.56(\mathrm{b}),$ though it uses additional transistors, has in fact less total area and lower propagation delay because it uses NOR gates with lower fan-in. Assuming that the transistors in both circuits are properly sized to provide each gate with a current-driving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have $\mathrm{a}(W / L)_{n}$ ratio of $0.27 \mu \mathrm{m} / 0.18 \mu \mathrm{m}$ and a $(W / L)_{p}$ ratio of $0.54 \mu \mathrm{m} / 0.18 \mu \mathrm{m}$.
Manish J.
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