Question

1. You are given the following SystemVerilog code of a synchronous circuit: module q1 ( input logic CK , input logic RN , input logic UD , input logic [3:0] MV , output logic MF , output logic [3:0] CV ); assign MF = (CV == MV); assign always_ff @ (posedge CK, negedge RN ) if (!RN) CV <= 0; else if ( UD ) if (CV == 0) CV <= MV; else CV <= CV - 1; else if (MF) CV <= 0; else CV <= CV + 1; endmodule

          1. You are given the following SystemVerilog code of a synchronous circuit:
module q1 (
input logic CK ,
input logic RN ,
input logic UD ,
input logic [3:0] MV ,
output logic MF ,
output logic [3:0] CV
);
assign MF = (CV == MV);
assign
always_ff @ (posedge CK, negedge RN )
if (!RN) CV <= 0;
else if ( UD )
if (CV == 0) CV <= MV;
else CV <= CV - 1;
else
if (MF) CV <= 0;
else CV <= CV + 1;
endmodule

1. You are given the following SystemVerilog code of a synchronous circuit:
module q1 (
input logic CK ,
input logic RN ,
input logic UD ,
input logic [3:0] MV ,
output logic MF ,
output logic [3:0] CV
);
assign MF = (CV == MV);
assign
alwaysff @ (posedge CK, negedge RN )
if (!RN) CV <= 0;
else if ( UD )
if (CV == 0) CV <= MV;
else CV <= CV - 1;
else
if (MF) CV <= 0;
else CV <= CV + 1;
endmodule

Added by Sherry C.

University Physics with Modern Physics

Hugh D. Young 14th Edition

Instant Answer

Solved by Expert Vishal Gupta

Step 1

The module `q1` has the following inputs: - `CK` (clock signal) - `RN` (reset signal) - `UD` (up/down signal) - `CV` (current value) Show more…

Show all steps

Thanks for your feedback!

You are given the following SystemVerilog code of a synchronous circuit: module q1( input logic CK, input logic RN, input logic UD, input logic [3:0] output logic MF, output logic [3:0] CV ); assign MF = (CV == MV); always_ff @ (posedge CK, negedge RN) if (!RN) CV <= 0; else if (UD) if (CV == 0) CV <= MV; else CV <= CV - 1; else if (MF) CV <= 0; else CV <= CV + 1; endmodule