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Computation Structures

Stephen A Ward, Robert H Halstead

Chapter 3

Combinational Devices and Circuits - all with Video Answers

Educators


Chapter Questions

Problem 1

Give a canonical sum-of-products expression for the Boolean function described by each truth table in figure 3.14 .

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Problem 2

Give a simplified sum-of-products expression for the Boolean function described by each truth table in figure 3.14 .

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Problem 3

Give a truth table for each of the following logical expressions.
A. $A \cdot \overline{B+C}$.
CAN'T COPY
CAN'T COPY
B. $(A+\bar{B}) \cdot \overline{A \cdot B \cdot C}+D$.
C. $A+B \cdot(C+\bar{D})$.
D. $(\bar{A}+B) \cdot(A+C)$.
E. $A+B \cdot C \cdot \bar{D}$.
F. $\overline{\bar{B}+\overline{(C+\overline{(D+C+A)}})}+\overline{(\bar{D}+B+\bar{A})}$.
G. $\overline{(\bar{A}+B \cdot \bar{D}) \cdot(B+\bar{C}) \cdot \overline{\bar{B} \cdot C \cdot D}}$.
H. $A \cdot B+\bar{A} \cdot(C+D)$.

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00:35

Problem 4

Give a simplified sum-of-products expression for each expression in problem 3.3.

James Kiss
James Kiss
Numerade Educator
01:53

Problem 5

Synthesize a circuit using only NAND gates for each expression in problem 3.3. (Omit expressions C and D, whose synthesis appears as example 3 in this chapter.)

Adriano Chikande
Adriano Chikande
Numerade Educator

Problem 6

Synthesize a circuit using only NOR gates for each expression in problem 3.3. (Omit expression E, whose synthesis appears as example 4 in this chapter.)

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01:26

Problem 7

Give a truth table for each circuit in figure 3.15.

Varsha Aggarwal
Varsha Aggarwal
Numerade Educator
01:20

Problem 8

Give a logical expression for each circuit in figure 3.15.

Vishal Gupta
Vishal Gupta
Numerade Educator
04:10

Problem 9

For each circuit in figure 3.15, draw a circuit that computes the same logic function but contains only OR gates and inverters.

Nishant Kumar
Nishant Kumar
Numerade Educator

Problem 10

Do the following for each circuit in figure 3.15:
(a)CAN'T COPY
(b)CAN'T COPY
(c)CAN'T COPY
(d)CAN'T COPY

$\bullet$ Draw a Karnaugh map, circling all prime implicants.
$\bullet$ Write a minimal sum-of-products expression, including only as many prime implicants as necessary.
$\bullet$ Synthesize a logic circuit based on this expression, using only AND gates, OR gates, and inverters.
$\bullet$ Identify hazards, if any, in the circuit drawn in the previous answer, indicating the hazard-producing transitions on your Karnaugh map.
$\bullet$ For each circuit containing one or more hazards, synthesize a hazard-free circuit that computes the same logic function.

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Problem 11

For each Karnaugh map in figure 3.16, show the minimum number of prime implicants needed to cover all the $1 \mathrm{~s}$ in the function. Indicate any hazards that are present if only the prime implicants that you identified are used.

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05:06

Problem 12

Repeat problem 3.10 , starting with the logical expressions in figure 3.10 instead of the circuits in figure 3.15 .

Amit Srivastava
Amit Srivastava
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Problem 13

Timing and Hazards:
Consider the following combinational circuit:
A. Suppose that each component in the circuit has a propagation delay of exactly $10 \mathrm{~ns}$ and negligible rise and fall times. Suppose initially that all four inputs are at 1 for a long time, and then the input $D$ changes to 0 . Fill in the following waveforms, and circle any glitches in the output $Q$ due to hazards.
B. Show how to eliminate the hazard(s) using a Karnaugh map and adding the least number of prime implicant(s).
C. Redraw the circuit and show the least additional hardware needed to implement the hazard-correcting implicants, using only NOTs and two-input ANDs and ORs.
D. Explain in words from your circuit diagram why any glitches of the original circuit have been eliminated.

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03:45

Problem 14

How many Boolean functions of four variables are there? Of $n$ variables?

WZ
Wen Zheng
Numerade Educator

Problem 15

Suppose you need to implement the function $\overline{A \cdot B}$, but all you have available is a three-input NAND. To what should the third input be connected so the output is still $\overline{A \cdot B}$ ?

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01:33

Problem 16

A certain two-input gate computes the exclusive-OR function using negative logic. What function does the same gate compute using positive logic?

Manik Pulyani
Manik Pulyani
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Problem 17

Is there a Boolean function that cannot be realized using only AND and OR gates? If so, give a simple example; if not, explain.

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02:32

Problem 18

Is it possible for a one-input, one-output combinational circuit built entirely of two-input NAND gates to contain a hazard? Either draw such a circuit or explain why one cannot be built.

Adriano Chikande
Adriano Chikande
Numerade Educator
02:32

Problem 19

Is it possible for a combinational circuit built entirely of AND and OR gates to contain a hazard? Either draw such a circuit or explain why one cannot be built.

Adriano Chikande
Adriano Chikande
Numerade Educator

Problem 20

Suppose you are shown this circuit:
Without any analysis-just by looking at the circuit-you should be able to tell whether it does or does not have a hazard. Explain how you can do this and indicate whether or not this circuit has a hazard. (You can assume that each individual gate is hazard-free.)

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Problem 21

Recall the discussion of the completeness of the NAND and NOR functions.
A. Referring to figure 3.2, identify which other two-argument Boolean functions are complete in the same sense. (Hint: Could a function be complete if its outputs are independent of one or both of its inputs?) Since NAND is complete, we can demonstrate the completeness of another Boolean function $f$ by showing how to implement NAND using only $f$ and the constants 1 and 0 . Use the notation $f_n$ to denote the function numbered $n$ in figure 3.2. For example, the completeness of the NOR function, $f_8$, can be demonstrated as follows:
$$
\mathrm{NAND}(A, B)=f_8\left(f_8\left(f_8(A, 0), f_8(B, 0)\right), 0\right) .
$$
B. Give a definition of NAND in terms of each of the other complete functions. Do the same for NOR.
C. Which of the sixteen two-input Boolean functions are complete assuming that constants are not available?
D. If you had to build a computer out of just one type of gate, would the NAND gate be preferred over the AND gate? Why or why not?

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Problem 22

A binary-to-seven-segment decoder takes 4 bits of input and produces seven outputs, one for each "segment" in a standard display:
Given the appropriate binary input, this display produces outputs that light up the display in the following manner:
We are interested in the circuit that produces the signal for the segment numbered 3 (a 1 turns a segment on; a 0 turns it off):
A. Construct a Karnaugh map for segment 3.
B. Write a minimal sum-of-products expression for segment 3 in terms of the inputs $a_0, a_1, a_2$, and $a_3$.
C. Draw a circuit that implements this expression using AND and OR gates and inverters.
D. Does your circuit contain hazards? If so, indicate the transitions on which these hazards occur on the Karnaugh map of part A.

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Problem 23

A common approach to the addition of $n$-bit binary numbers uses $n$ cascaded combinational modules, each a 1-bit adder (conventionally called a full adder). Full-adder modules can be combined as follows to implement a circuit that adds the $n$-bit unsigned binary value $A$ to the $n$-bit unsigned binary value $B$, yielding the n-bit sum $S$ ( $A_0$ designates the low-order bit of $A$, and $A_{n-1}$ the high-order bit):

A. What information is carried by the $C_{\mathrm{i}}$ input to each full adder? By the $C_{\mathrm{o}}$ output?
B. Suppose the $C_{\mathrm{i}}$ input to the low-order full adder is connected to logical 1 rather than logical 0 . Describe the relationship of the binary number $S$ to the input numbers $A$ and $B$ under these circumstances.
C. Give truth tables for each of the outputs $S$ and $C_{\mathrm{o}}$ for the full-adder module in terms of its inputs $A, B$, and $C_{\mathrm{i}}$. Draw Karnaugh maps for each output.
D. Draw a circuit diagram for a full-adder module, using AND, OR, NAND, XOR, and inverter modules. Try to minimize the number of component modules in your design. (Hint: You'll find an XOR gate useful.)
E. Assuming a $t_{\mathrm{pd}}$ of $10 \mathrm{~ns}$ for each module, what propagation delay should be specified for the full adder? For the $n$-bit adder?
F. Propose an addition to the circuit to produce a single output bit $U$ that carries a 1 if and only if the addition of the unsigned numbers $A$ and $B$ overflows the $n$-bit result $S$.
G. What modifications are necessary to make the $n$-bit adder properly add two signed numbers represented in 2's complement binary? Explain.
H. Propose an addition to your (perhaps modified) circuit to produce an output $V$ that carries a 1 if and only if the addition of the signed numbers $A$ and $B$ overflows the $n$-bit result $S$.

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07:57

Problem 24

The Massachusetts Bay Transportation Authority (MBTA) has just awarded you a contract to revamp the signaling system on its Green Line. You have decided upon the following basic approach: Each section of track will have a sensor to determine whether there is a train in that section and a signal with red, yellow, and green lights. You want the light in a track section to show red if there is a train in the very next section, yellow if there is no train in the next section but the section after that is occupied, and green otherwise. You decide to place a logic module, shown schematically below, under each section of track:
Tracks are one-way only, and trains move left to right relative to the track control module. The outputs $G, Y$, and $R$ should be a 1 to light the green, yellow, and red signals, respectively, for this section of track. The input $P$ is 1 if there is a train in this section. The signals $A_{\mathrm{i}}$ and $B_{\mathrm{i}}$ are received from the next section, and outputs $A_{\mathrm{o}}$ and $B_{\mathrm{o}}$ are passed back to the previous section. You may do with these what you like, but there are only two wires available, and you may not add more.
A. Design the logic for this box to implement the signaling function. Describe what use you have made of lines $A$ and $B$.
B. Under switches that merge two incoming tracks into one outgoing track, you will need to put a special kind of module:
This module operates like a regular track control module except that it signals red in the previous section (and yellow in the section before that) to trains coming from the direction the switch is not currently set to accept. The input $S$ is 1 if the switch is set straight, 0 if it is tumed. Give a logic diagram for this new module. You need not worry about logic modules for switches that split one incoming track into two outgoing tracks.

Keshav Singh
Keshav Singh
Numerade Educator