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Digital Design and Verilog HDL Fundamentals

Joseph Cavanagh

Chapter 3

Combinational Logic - all with Video Answers

Educators


Chapter Questions

01:22

Problem 1

Given the logic diagram shown below using NAND gates, obtain the Karnaugh map, the equation in a sum-of-products form, and the equation in a sum-ofproducts decimal notation.
(FIGURE CAN'T COPY)

Adriano Chikande
Adriano Chikande
Numerade Educator
01:21

Problem 2

Analyze the logic diagram shown below by obtaining the equation for output $z_1$. Then verify the answer by means of a truth table.
(FIGURE CAN'T COPY)

Jay Patel
Jay Patel
Numerade Educator
01:21

Problem 3

Analyze the logic diagram shown below by obtaining the equation for output $z_1$. Then verify the answer by means of a truth table.
(FIGURE CAN'T COPY)

Jay Patel
Jay Patel
Numerade Educator

Problem 4

A majority circuit is a logic circuit whose output is a logic 1 (high) if the majority of the inputs are a logic 1 (high); otherwise, the output is a logic 0 (low). Obtain the Boolean equation for $z_1\left(x_1, x_2, x_3\right)$ that is implemented by the majority circuits shown below. The equation for $z_1$ is to be in a minimum sumof-products form.
(FIGURE CAN'T COPY)

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02:49

Problem 5

Obtain the equation for output $z_1$ in a sum-of-products notation for the logic diagram shown below.
(FIGURE CAN'T COPY)

Sriram Soundarrajan
Sriram Soundarrajan
Numerade Educator
02:31

Problem 6

Given the logic diagram shown below, obtain the equation for output $z_1$ in a product-of-sums form.
(FIGURE CAN'T COPY)

Jay Patel
Jay Patel
Numerade Educator

Problem 7

Obtain the minimum Boolean expression for the following logic circuit in a sum-of-products form.
(FIGURE CAN'T COPY)

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Problem 8

Given the two multiplexers and inputs as shown below, complete the following truth table for output $z_1$ as a function of the inputs $I n_0, I n_1, I n_2$, and $I n_3$ -
$$
\begin{array}{ccc}
\hline x_1 & x_2 & z_1 \\
\hline \hline 0 & 0 & \\
0 & 1 & \\
1 & 0 & \\
1 & 1 & \\
\hline
\end{array}
$$
(FIGURE CAN'T COPY)

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01:45

Problem 9

Given the following equation for $z_1$, design the logic circuit using AND gates and $\mathrm{OR}$ gates.
$$
z_1=\left[x_1 x_2^{\prime}+\left(x_1^{\prime}+x_2+x_3\right)\right]\left[\left(x_1^{\prime}+x_2+x_3\right)+x_4 x_5^{\prime}\right]
$$

Mirza  Aslam Beig
Mirza Aslam Beig
Numerade Educator
13:09

Problem 10

Minimize the following equation using Boolean algebra to obtain a sum-ofproducts expression, then implement the expression using NAND gates. Assume that only active-high inputs are available. Output $z_1$ is asserted high.
$$
z_1=x_1^{\prime} x_2+x_3 x_4+\left(x_1+x_2\right)^{\prime}\left[x_1 x_3 x_4+\left(x_2 x_5\right)^{\prime}\right]
$$

Chris Trentman
Chris Trentman
Numerade Educator

Problem 11

Implement the logic functions shown below using any type of logic gates. The inputs are available in both high and low assertions; the outputs are asserted low. Minimize the equations, if possible, to use the fewest number of gates.
$$
\begin{aligned}
& z_1=x_2^{\prime} x_4^{\prime} \\
& z_2=x_1^{\prime} x_2+x_1^{\prime} x_2^{\prime} x_4^{\prime} \\
& z_3=x_1 x_2^{\prime} x_3^{\prime} x_4^{\prime}+x_1 x_2 x_3^{\prime} x_4+x_1^{\prime} x_2 x_3 x_4+x_1^{\prime} x_2^{\prime} x_3 x_4^{\prime}
\end{aligned}
$$

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Problem 12

Design a logic circuit that is represented by the Karnaugh map shown below. Use only NOR logic. The inputs are available in both high and low assertion.
(TABLE CAN'T COPY)

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Problem 13

Design a logic circuit that is represented by the Karnaugh map shown below. Use only NAND logic. The inputs are available in both high and low assertion.
(TABLE CAN'T COPY)

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01:23

Problem 14

Synthesize a logic circuit that will control the interior lighting of a building. The building contains four rooms separated by removable partitions. There is one switch in each room which, in conjunction with the other switches, provides the following methods of control:
(a) All partitions are closed forming four separate rooms. Each switch controls only the lights in its respective room.
(b) All partitions are open forming one large room. Each switch controls all the lights in the building; that is, when the lights are on, they can be turned off by any switch. Conversely, when the lights are off, they can be turned on by any switch.
(c) Two of the partitions are closed forming three rooms. The middle partition is open, so that the middle room is larger than the other two rooms. Each switch controls the lights in its room only.
(d) The middle partition is closed forming two rooms. Each switch controls the lights in its room only.
The switch method outlined above is referred to as four-way switching. This technique provides control of one set of lights by one or more switches. Implement the circuit using 4:1 multiplexers and additional logic functions. The output of the multiplexers connect to the lights. The partitions are labeled $\mathrm{P} 1, \mathrm{P} 2$, and $\mathrm{P} 3$; the lights are labeled $\mathrm{L} 1, \mathrm{~L} 2, \mathrm{~L} 3$, and L4; the switches are labeled $\mathrm{S} 1, \mathrm{~S} 2, \mathrm{~S} 3$, and $\mathrm{S} 4$.

Sriram Soundarrajan
Sriram Soundarrajan
Numerade Educator

Problem 15

Implement the Kamaugh map shown below using a linear-select multiplexer and additional logic gates. Use the least amount of logic.
(TABLE CAN'T COPY)

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Problem 17

Given the Kamaugh map shown below, obtain the minimized data input equations for a nonlinear-select multiplexer. Show the data input equations for each permutation of the Karnaugh map, then implement the design using the equations with the least amount of logic.
(TABLE CAN'T COPY)

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02:22

Problem 18

The truth table shown below represents the logic for output $z_1$ of a combinational logic circuit. Implement the logic using a nonlinear-select multiplexer and additional logic gates, if necessary. Use the least amount of logic.
$$
\begin{array}{ccccc}
\hline y_1 & y_2 & y_3 & y_4 & z_1 \\
\hline \hline 0 & 0 & 0 & 0 & x_1^{\prime} \\
0 & 0 & 0 & 1 & 1 \\
0 & 0 & 1 & 0 & x_1^{\prime} \\
0 & 0 & 1 & 1 & 1 \\
\hline 0 & 1 & 0 & 0 & - \\
0 & 1 & 0 & 1 & - \\
0 & 1 & 1 & 0 & x_1 \\
0 & 1 & 1 & 1 & 0 \\
\hline \text { Continued on next page) } \\
\hline
\end{array}
$$
$$
\begin{array}{ccccc}
\hline y_1 & y_2 & y_3 & y_4 & z_1 \\
\hline \hline 1 & 0 & 0 & 0 & 0 \\
1 & 0 & 0 & 1 & 0 \\
1 & 0 & 1 & 0 & - \\
1 & 0 & 1 & 1 & 0 \\
\hline 1 & 1 & 0 & 0 & 0 \\
1 & 1 & 0 & 1 & 0 \\
1 & 1 & 1 & 0 & - \\
1 & 1 & 1 & 1 & - \\
\hline
\end{array}
$$

AK
Ankur Khosla
Numerade Educator
01:45

Problem 19

Given the following Karnaugh map, implement the function for $z_1$ using a $4: 1$ multiplexer and additional logic gates, if necessary.
(TABLE CAN'T COPY)

Mirza  Aslam Beig
Mirza Aslam Beig
Numerade Educator

Problem 20

Design an 8-bit odd parity generator. The parity bit is appended to the 8-bit byte of data such that the number of $1 \mathrm{~s}$ in the nine bits (eight data bits plus the parity bit) is odd. A parity generator can be implemented easily by modulo-2 addition. The truth table for modulo-2 addition (exclusive-OR) is shown below. The output $z_1$ is a logic 1 if there is an odd number of $1 \mathrm{~s}$ on the inputs. Therefore, the output can be inverted to obtain odd parity for the byte of data.
$$
\begin{array}{ccc}
\hline x_1 & x_2 & z_1 \\
\hline \hline 0 & 0 & 0 \\
0 & 1 & 1 \\
1 & 0 & 1 \\
1 & 1 & 0 \\
\hline
\end{array}
$$

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Problem 21

Design an 8-bit odd parity checker.

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Problem 22

A logic circuit has two control inputs $c_1$ and $c_0$, two data inputs $x_1$ and $x_2$, and one output $z_1$. The circuit operates as follows:
If $c_1 c_0=00$, then $z_1=0$
If $c_1 c_0=01$, then $z_1=x_2$
If $c_1 c_0=10$, then $z_1=x_1$
If $c_1 c_0=11$, then $z_1=1$
Derive a truth table for output $z_1$. Then use a Karnaugh map to obtain the Boolean expression for $z_1$ in a sum-of-products form and implement the logic using NAND gates.

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Problem 23

Synthesize a 4-bit comparator using any logic primitives, including exclusiveNOR functions. There are two 4-bit unsigned binary operands, $A=a_3 a_2 a_1 a_0$ and $B=b_3 b_2 b_1 b_0$, where $a_0$ and $b_0$ are the low-order bits of $A$ and $B$, respectively. There are three outputs:
$$
A<B, A=B, A>B
$$

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Problem 24

Design a high-speed shift unit that will shift an 8-bit operand right or left zero, one, two, or three bit positions. Use $4: 1$ multiplexers as the shifting elements and any additional logic functions. The operand is unsigned; therefore, this will be a logical shift. Zeroes are shifted into the vacated high-order bit positions during a right shift operation. Zeroes are shifted into the vacated loworder bit positions during a left shift operation. Assume that a logic 0 is equivalent to a ground potential.
$$
\begin{array}{|l|l|l|l|l|l|l|l|}
\hline 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
\hline
\end{array}
$$

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Problem 25

Use two 4-bit comparators to determine if a modulo-16 number meets the following requirements: $4>N>11$. Use NAND logic only. If the number meets the requirements, then the output of the logic circuit is a high logic level.

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