Digital integrated circuits : A Design perspective

Jan M Rabaey; Anantha P Chandrakasan; Borivoje Nikolić

Chapter 6 DESIGNING COMBINATIONAL LOGIC GATES IN CMOS - all with Video Answers

Educators

Chapter Questions

Problem 1

[E, None, 4.2] Implement the equation $X=((\bar{A}+\bar{B})(\bar{C}+\bar{D}+\bar{E})+\bar{F}) \bar{G}$ using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS $W / L=2$ and PMOS $W / L=6$. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance?

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Problem 2

Implement the following expression in a full static CMOS logic fashion using no more than 10 transistors:
$$
\bar{Y}=(A \cdot B)+(A \cdot C \cdot E)+(D \cdot E)+(D \cdot C \cdot B)
$$

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Problem 3

Consider the circuit of Figure 6.1.
Figure 6.1 CMOS combinational logic gate.
a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an $\mathrm{NMOS} W / L=4$ and PMOS $W / L=8$.
b. What are the input patterns that give the worst case $t_{p w}$ and $t_{p L H}$ State clearly what are the initial input patterns and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes.
c. Verify part (b) with SPICE. Assume all transistors have minimum gate length $(0.25 \mu \mathrm{m})$.
d. If $\mathrm{P}(\mathrm{A}=1)=0.5, \mathrm{P}(\mathrm{B}=1)=0.2, \mathrm{P}(\mathrm{C}=1)=0.3$ and $\mathrm{P}(\mathrm{D}=1)=1$, determine the power dissipation in the logic gate. Assume $V_{D D}=2.5 \mathrm{~V}, C_{\text {eat }}=30 \mathrm{fF}$ and $f_{C L K}=250 \mathrm{MHz}$

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Problem 4

$[\mathrm{M}$, None, 4.2] CMOS Logic
a. Do the following two circuits (Figure 6.2) implement the same logic function? If yes, what is that logic function? If no, give Boolean expressions for both circuits.
b. Will these two circuits' output resistances always be equal to each other?
c. Will these two circuits' rise and fall times always be equal to each other? Why or why not?

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Problem 5

[E, None, 4.2] The transistors in the circuits of the preceding problem have been sized to give an output resistance of $13 \mathrm{k} \Omega$ for the worst-case input pattern. This output resistance can vary, however, if other patterns are applied.
a. What input patterns $(A-E)$ give the lowest output resistance when the output is low? What is the value of that resistance?
b. What input patterns $(A-E)$ give the lowest output resistance when the output is high? What is the value of that resistance?

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06:05

Problem 6

[E, None, 4.2] What is the logic function of circuits $\mathrm{A}$ and $\mathrm{B}$ in Figure 6.3? Which one is a dual network and which one is not? Is the nondual network still a valid static logic gate? Explain. List any advantages of one configuration over the other.
Figure 6.3 Two logic functions.

Mirza Aslam Beig

Numerade Educator

Problem 7

[E, None, 4.2] Compute the following for the pseudo-NMOS inverter shown in Figure 6.4 :
a. $V_{O L}$ and $V_{O H}$
b. $N M_L$ and $N M_H$
c. The power dissipation: (1) for $V_{\text {mi }}$ low, and (2) for $V_{\text {in }}$ high
d. For an output load of $1 \mathrm{pF}$, calculate $t_{p L H}, t_{p N L L}$, and $t_F$ Are the rising and falling delays equal? Why or why not?

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Problem 8

$[\mathrm{M}$, SPICE, 4.2] Consider the circuit of Figure 6.5.
a. What is the output voltage if only one input is high? If all four inputs are high?
b. What is the average static power consumption if, at any time, each input turns on with an (independent) probability of 0.5 ? 0.1 ?
c. Compare your analytically obtained results to a SPICE simulation.
Figure 6.5 Pseudo-NMOS gate.

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Problem 9

$[\mathrm{M}$, None, 4.2$]$ Implement $F=A \overline{B C}+\bar{A} C D$ (and $\bar{F}$ ) in DCVSL. Assume $A, B, C, D$, and their complements are available as inputs. Use the minimum number of transistors.

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Problem 10

[E, Layout, 4.2] A complex logic gate is shown in Figure 6.6.
a. Write the Boolean equations for outputs $F$ and $G$. What function does this circuit implement?
b. What logic family does this circuit belong to?
c. Assuming $W / L=0.5 \mathrm{u} / 0.25 \mathrm{u}$ for all nmos transistors and $W / L=2 \mathrm{u} / 0.25 \mathrm{u}$ for the pmos transistors, produce a layout of the gate using Magic. Your layout should conform to the following datapath style: (1) Inputs should enter the layout from the left in polysilicon; (2) The outputs should exit the layout at the right in polysilicon (since the outputs would probably be driving transistor gate inputs of the next cell to the right); (3) Power and ground lines should run vertically in metal 1.
d. Extract and netlist the layout. Load both outputs (F,G) with a $30 \mathrm{fF}$ capacitance and simulate the circuit. Does the gate function properly? If not, explain why and resize the transistors so that it does. Change the sizes (and areas and perimeters) in the HSPICE netlist.

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02:19

Problem 11

Design and simulate a circuit that generates an optimal differential signal as shown in Figure 6.7. Make sure the rise and fall times are equal.

Arpit Gupta

Numerade Educator

Problem 12

What is the function of the circuit in Figure 6.8?

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Problem 13

Implement the function $S=A B C+A \overline{B C}+\overline{A B} C+\bar{A} B \bar{C}$, which gives the sum of two inputs with a carry bit, using NMOS pass transistor logic. Design a DCVSL gate which implements the same function. Assume $A, B, C$, and their complements are available as inputs

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Problem 14

Describe the logic function computed by the circuit in Figure 6.9. Note that all transistors (except for the middle inverters) are NMOS. Size and simulate the circuit so that it achieves a $100 \mathrm{ps}$ delay ( $50-50$ ) using $0.25 \mu \mathrm{m}$ devices, while driving a $100 \mathrm{fF}$ load on both differential outputs. $\left(V_{D D}=2.5 \mathrm{~V}\right)$ Assume $A, B$ and their complements are available as inputs.
For the drain and source perimeters and areas you can use the following approximations: $\mathrm{AS}=\mathrm{AD}=\mathrm{W}^* 0.625 \mathrm{u}$ and $\mathrm{PS}=\mathrm{PD}=\mathrm{W}+1.25 \mathrm{u}$.

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Problem 15

$[\mathrm{M}$, None. 4.2] Figure 6.10 contains a pass-gate logic network.
a. Determine the truth table for the circuit. What logic function does it implement?
b. Assuming 0 and $2.5 \mathrm{~V}$ inputs, size the PMOS transistor to achieve a $V_{o L}=0.3 \mathrm{~V}$
c. If the PMOS were removed, would the circuit still function correctly? Does the PMOS transistor serve any useful purpose?
Figure 6.10 Pass-gate network.

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01:11

Problem 16

[M, None, 4.2] This problem considers the effects of process scaling on pass-gate logic.
a. If a process has a $t_{h u}$ of $0.4 \mathrm{~ns}, R_{e q}$ of $8 \mathrm{k} \Omega$, and $C$ of $12 \mathrm{fF}$, what is the optimal number of stages between buffers in a pass-gate chain?
b. Suppose that, if the dimension of this process are shrunk by a factor $S, R_{e q}$ scales as $1 / S^2, C$ scales as $1 / S$, and $t_{\text {hop }}$ scales as $1 / S^2$. What is the expression for the optimal number of buffers as a function of $S$ ? What is this value if $S=2$ ?

Kratika Bhadauria

Numerade Educator

Problem 17

[C, None, 4.2] Consider the circuit of Figure 6.11. Let $C_x=50 \mathrm{fF}, M$, has $W / L=0.375 / 0.375$, $M_n$ has $W / L_{e f f}=0.375 / 0.25$. Assume the output inverter doesn't switch until its input equals $V_{n 0} / 2$.
a. How long will it take $M_n$ to pull down node $x$ from $2.5 \mathrm{~V}$ to $1.25 \mathrm{~V}$ if $\ln$ is at $0 \mathrm{~V}$ and $B$ is at $2.5 \mathrm{~V} ?$
b. How long will it take $M_n$ to pull up node $x$ from $0 \mathrm{~V}$ to $1.25 \mathrm{~V}$ if $V_h$ is $2.5 \mathrm{~V}$ and $V_R$ is $2.5 \mathrm{~V}^{\prime}$ ?
c. What is the minimum value of $V_R$ necessary to pull down $V_x$ to $1.25 \mathrm{~V}$ when $V_{\text {m }}=0 \mathrm{~V}$ ?

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Problem 18

Pass Transistor Logic
Consider the circuit of Figure 6.12 . Assume the inverter switches ideally at $\mathrm{V}_{\mathrm{Do}} / 2$, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem.
a. What is the logic function performed by this circuit?
b. Explain why this circuit has non-zero static dissipation.
c. Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor.
d. Implement the same circuit using transmission gates.
e. Replace the pass-transistor network in Figure 6.12 with a pass transistor network that computes the following function: $x=A B C$ at the node $\mathrm{x}$. Assume you have the true and complementary versions of the three inputs $A, B$ and $C$.

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Problem 19

[M, None, 4.3] Sketch the waveforms at $x, y$, and $z$ for the given inputs (Figure 6.13). You may approximate the time scale, but be sure to compute the voltage levels. Assume that $V_T=0.5 \mathrm{~V}$ when body effect is a factor.

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04:24

Problem 20

[E, None, 4.3] Consider the circuit of Figure 6.14.
a. Give the logic function of $x$ and $y$ in terms of $A, B$, and $C$. Sketch the waveforms at $x$ and $y$ for the given inputs. Do $x$ and $y$ evaluate to the values you expected from their logic functions? Explain.
b. Redesign the gates using $n p-C M O S$ to eliminate any race conditions. Sketch the waveforms at $x$ and $y$ for your new circuit.

Gabriel Eduok

Numerade Educator

Problem 21

$[\mathrm{M}$, None, 4.3] Suppose we wish to implement the two logic functions given by $F=A+B+C$ and $G=A+B+C+D$. Assume both true and complementary signals are available.
a. Implement these functions in dynamic CMOS as cascaded $\phi$ stages so as to minimize the total transistor count.
b. Design an $n p$-CMOS implementation of the same logic functions. Does this design display any of the difficulties of part (a)?

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01:26

Problem 22

Consider a conventional 4-stage Domino logic circuit as shown in Figure 6.15 in which all precharge and evaluate devices are clocked using a common clock $\phi$. For this entire problem, assume that the pulldown network is simply a single NMOS device, so that each Domino stage consists of a dynamic inverter followed by a static inverter. Assume that the precharge time, evaluate time, and propagation delay of the static inverter are all $T / 2$. Assume that the transitions are ideal (zero rise/fall times).
a. Complete the timing diagram for signals $O u t_l, O u t_2, O u t_3$ and $O u t_f$, when the $I N$ signal goes high before the rising edge of the clock $\phi$. Assume that the clock period is $10 \mathrm{~T}$ time units.
b. Suppose that there are no evaluate switches at the 3 latter stages. Assume that the clock $\phi$ is initially in the precharge state ( $\phi=0$ with all nodes settled to the correct precharge states), and the block enters the evaluate period $(\phi=1)$. Is there a problem during the evaluate period, or is there a benefit? Explain.
c. Assume that the clock $\phi$ is initially in the evaluate state $(\phi=1)$, and the block enters the precharge state $(\phi=0)$. Is there a problem, or is there any benefit, if the last three evaluate switches are removed? Explain.

Andreas Papavassiliou

Numerade Educator

01:26

Problem 23

$[\mathrm{C}$, Spice, 4.3] Figure 6.16 shows a dynamic CMOS circuit in Domino logic. In determining source and drain areas and perimeters, you may use the following approximations: $A D=A S=$ $W \times 0.625 \mu \mathrm{m}$ and $P D=P S=W+1.25 \mu \mathrm{m}$. Assume $0.1 \mathrm{~ns}$ rise/fall times for all inputs, including the clock. Furthermore, you may assume that all the inputs and their complements are available, and that all inputs change during the precharge phase of the clock cycle.
a. What Boolean functions are implemented at outputs $F$ and $G$ ? If $A$ and $B$ are interpreted as two-bit binary words, $A=A_1 A_0$ and $B=B_1 B_0$, then what interpretation can be applied to output $G$ ?
b. Which gate ( 1 or 2 ) has the highest potential for harmful charge sharing and why? What sequence of inputs (spanning two clock cycles) results in the worst-case charge-sharing scenario? Using SPICE, determine the extent to which charge sharing affects the circuit for this worst case.

Andreas Papavassiliou

Numerade Educator

Problem 24

[M, Spice, 4.3] In this problem you will consider methods for eliminating charge sharing in the circuit of Figure 6.16. You will then determine the performance of the resulting circuit.
a. In problem 24 you determined which gate ( 1 or 2 ) suffers the most from charge sharing. Add a single $2 / 0.25$ PMOS precharge transistor (with its gate driven by the clock $\phi$ and its source connected to $V_{D D}$ ) to one of the nodes in that gate to maximally reduce the chargesharing effect. What effect (if any) will this addition have on the gate delay? Use SPICE to demonstrate that the additional transistor has eliminated charge sharing for the previously determined worst-case sequence of inputs.
b. For the new circuit (including additional precharge transistor), find the sequence of inputs (spanning two clock cycles) that results in the worst-case delay through the circuit.
Remember that precharging is another factor that limits the maximum clocking frequency of the circuit, so your input sequence should address the worst-case precharging delay.
c. Using SPICE on the new circuit and applying the sequence of inputs found in part (b), find the maximum clock frequency for correct operation of the circuit. Remember that the precharge cycle must be long enough to allow all precharged nodes to reach $\sim 90 \%$ of their final values before evaluation begins. Also, recall that the inputs $(A, B$ and their complements) should not begin changing until the clock signal has reached $0 \mathrm{~V}$ (precharge phase), and they should reach their final values before the circuit enters the evaluation phase.

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01:26

Problem 25

[C, None, 4.2-3] For this problem, refer to the layout of Figure 6.17.
a. Draw the schematic corresponding to the layout. Include transistor sizes.
b. What logic function does the circuit implement? To which logic family does the circuit belong?
c. Does the circuit have any advantages over fully complementary CMOS?
d. Calculate the worst-case $V_{O L}$ and $V_{O H}$.
e. Write the expresions for the area and perimeter of the drain and source for all of the FETs in terms of $\lambda$. Assume that the capacitance of shared diffuusions divides evenly between the sharing devices. Copy the layout into Magic, extract and simulate to find the worstcase $t_{\text {HHL }}$ time. For what input transition(s) does this occur? Name all of the parasitic capacitances that you would need to know to calculate this delay by hand (you do not need to perform the calculation).

Andreas Papavassiliou

Numerade Educator

Problem 26

[E, None, 4.4] Derive the truth table, state transition graph, and output transition probabilities for a three-input XOR gate with independent, identically distributed, uniform white-noise inputs.

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Problem 27

[C, None, 4.4] Figure 6.18 shows a two-input multiplexer. For this problem, assume independent, identically-distributed uniform white noise inputs.
a. Does this schematic contain reconvergent fan-out? Explain your answer.
b. Find the exact signal $\left(P_1\right)$ and transition $\left(P_{0 \rightarrow 1}\right)$ formulas for nodes $X, Y$, and $Z$ for: (1) a static, fully complementary CMOS implementation, and (2) a dynamic CMOS implementation.

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Problem 28

[M, None, 4.4] Compute the switching power consumed by the multiplexer of Figure 6.18 , assuming that all significant capacitances have been lumped into the three capacitors shown in the figure, where $C=0.3 \mathrm{pF}$. Assume that $V_{D D}=2.5 \mathrm{~V}$ and independent, identically-distributed uniform white noise inputs, with events occuring at a frequency of $100 \mathrm{MHz}$ Perform this calculation for the following:
a. A static, fully-complementary CMOS implementation
b. A dynamic CMOS implementation

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Problem 29

Consider the circuit shown Figure 6.19 .
a. What is the logic function implemented by this circuit? Assume that all devices (M1-M6) are $0.5 \mu \mathrm{m} / 0.25 \mu \mathrm{m}$
b. Let the drain current for each device (NMOS and PMOS) be $1 \mu \mathrm{A}$ for NMOS at $V_{G S}=V_T$ and PMOS at $V_{S G}=V_T$. What input vectors cause the worst case leakage power for each output value? Explain (state all the vectors, but do not evaluate the leakage). Ignore DIBL.
c. Suppose the circuit is active for a fraction of time $d$ and idle for $(I-d)$. When the circuit is active, the inputs arrive at $100 \mathrm{MHz}$ and are uniformly distributed $\left(\operatorname{Pr}_{(\mathrm{A}-1)}=0.5\right.$, $\left.\mathrm{Pr}_{(\mathrm{B}-1)}=0.5, \mathrm{Pr}_{(\mathrm{C}-1)}=0.5\right)$ and independent. When the circuit is in the idle mode, the inputs are fixed to one you chose in part (b). What is the duty cycle $d$ for which the active power is equal to the leakage power?

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