Chapter Questions
In Figure 7.1.3, we showed the design of an SR latch using NOR gates. Replace the NOR gates by NAND gates and construct the characteristic table of the latch. Replace the $S$ and $R$ labels by $X$ and $Y$, respectively.
Figure 7.1.3 of the design of an SR latch can be modified to include asynchronous preset and clear inputs. The inputs are used as inputs to the NOR gates. Modify the circuit design to include a preset and clear inputs.
Show the design of a gated SR latch using NAND gates only.
Construct the characteristic equations of the complement output ( $Q$ ) of a JK latch.
Show the design of a JK flip-flop using T flip-flops.
Show the design of a $\mathrm{T}$ flip-flop using $\mathrm{D}$ flip-flops.
Given that a clock cycle width is $10 \mathrm{~ns}$ and that the clock assumes a value of 1 for $2 \mathrm{~ns}$ of the cycle time. Determine the frequency of the clock. Determine the duty cycle.
Complete the timing diagram of the SR latch shown in Figure E.7.1. Assume the top NOR gate delay is $1 \mathrm{~ns}$ and the lower NOR gate delay is $2 \mathrm{~ns}$. Assume, initially, $Q=0$ and $Q=1$.FIGURE E7.1 can't copy
Show the design of a master-slave $\mathrm{T}$ flip-flop with changes occurring at the rising edge of the clock. Use block diagrams for the master and slave part of the flip-flop.
Show the design of a master-slave D flip-flop with changes occurring at the falling edge of the clock.
Given a sequential circuit with two JK flip-flops $X$ and $Y$, an external input $I$, output out, and with$$J_x=\mathrm{I}, K_x=I, \quad J_y=\mathrm{IX}, K_y=I X, \quad \text { OUT }=I X Y$$
Construct the characteristic equations of $X$ and $Y$.
Draw the circuit schematics corresponding to the equations given in the previous question.
Construct the state diagram of the circuit with equations given in question 7.11.
Given the circuit shown in the Figure E7.2(a) Find the excitation equations of the inputs to the flip-flops.(b) Find the characteristic equations of the flip-flops.(c) Construct the state diagram of the circuit.FIGURE E7.2 can't copy
Construct the three alternative characteristic tables of the circuit given in the previous question.
For the circuit given in Figure E7.2, determine the sequence of states and outputs on the input 0110011101 . Assume the initial state is $\mathrm{AB}=00$.FIGURE E7.2 can't copy
Given the circuit shown in the Figure E7.3. The circuit input is $x$ as shown. The top T flip-flop input is set to 1 .(a) Find the characteristic and output equations of the circuit.(b) Construct the state diagram of the circuit (note that the circuit represents a Moore circuit).FIGURE E7.3 can't copy
Complete the following timing diagram (Figure E7.4) of the circuit given in the previous question. Assume the changes occur on the rising edge of the clock (no delay). Assume the initial WZ value is 00.FIGURE E7.4 can't copy