Computer System Architecture

M. Morris Mano

Chapter 11 Input-Output Organization - all with Video Answers

Educators

Chapter Questions

Problem 1

The addresses assigned to the four registers of the I/O interface of Fig. 11-2 are equal to the binary equivalent of $12,13,14$, and 15 . Show the external circuit that must be connected between an 8-bit I/O address from the CPU and the CS, RS1, and RSO inputs of the interface.

Check back soon!

Problem 2

Six interface units of the type shown in Fig. 11-2 are connected to a CPU that uses an I/O address of eight bits. Each one of the six chip select (CS) inputs is connected to a different address line. Thus the high-order address line is connected to the CS input of the first interface unit and the sixth address line is connected to the CS input of the sixth interface unit. The two low-order address lines are connected to the RS1 and RSO of all six interface units. Determine the 8-bit address of each register in each interface.

Check back soon!

Problem 3

List four peripheral devices that produce an acceptable output for a person to understand.

Check back soon!

03:42

Problem 4

Write your full name in ASCII using eight bits per character with the leftmost bit always 0 . Include a space between names and a period after a middle initial.

Reynald Oliveria

Numerade Educator

Problem 5

What is the difference between isolated I/O and memory-mapped I/O? What are the advantages and disadvantages of each?

Check back soon!

Problem 6

Indicate whether the following constitute a control, status, or data transfer commands.
a. Skip next instruction if flag is set.
b. Seek a given record on a magnetic disk.
c. Check if I/O device is ready.
d. Move printer paper to beginning of next page.
e. Read interface status register.

Check back soon!

Problem 7

A commercial interface unit uses different names for the handshake lines associated with the transfer of data from the I/O device into the interface unit. The interface input handshake line is labeled STB (strobe), and the interface output handshake line is labeled IBF (input buffer full). A low-level signal on STB loads data from the I/O bus into the interface data register. A high-level signal on IBF indicates that the data item has been accepted by the interface. IBF goes low after an I/O read signal from the CPU when it reads the contents of the data register.
a. Draw a block diagram showing the CPU, the interface, and the I/O device together with the pertinent interconnections among the three units.
b. Draw a timing diagram for the handshaking transfer.
c. Obtain a sequence-of-events flowchart for the transfer from the device to the interface and from the interface to the CPU.

Check back soon!

Problem 8

A CPU with a 20-MHz clock is connected to a memory unit whose access time is $40 \mathrm{~ns}$. Formulate a read and write timing diagrams using a READ strobe and a WRITE strobe. Include the address in the timing diagram.

Check back soon!

Problem 9

The asynchronous communication interface shown in Fig. 11-8 is connected between a CPU and a printer. Draw a flowchart that describes the sequence of operations in the transmitter portion of the interface when the CPU sends characters to be printed.

Check back soon!

Problem 10

Give at least six status conditions for the setting of individual bits in the status register of an asynchronous communication interface.

Check back soon!

00:39

Problem 11

How many bits are there in the transmitter shift register of Fig. 11-8 when the interface is attached to a terminal that needs one stop bit? List the bits in the shift register when the letter $W$ is transmitted using ASCII with even parity.

Nick Johnson

Numerade Educator

01:27

Problem 12

How many characters per second can be transmitted over a 1200-baud line in each of the following modes? (Assume a character code of eight bits.)
a. Synchronous serial transmission.
b. Asynchronous serial transmission with two stop bits.
c. Asynchronous serial transmission with one stop bit.

Shelby Mohamed

Numerade Educator

Problem 13

Information is inserted into a FIFO buffer at a rate of $m$ bytes per second. The information is deleted at a rate of $n$ byte per second. The maximum capacity of the buffer is $k$ bytes.
a. How long does it take for an empty buffer to fill up when $m>n$ ?
b. How long does it take for a full buffer to empty when $m<n$ ?
c. Is the FIFO buffer needed if $m=n$ ?

Check back soon!

Problem 14

The bits in the control register of the FIFO shown in Fig. 11-9 are $F_1 F_2 F_3 F_4=0011$. Give the sequence of internal operations when an item is deleted from the FIFO and then a new item is inserted.

Check back soon!

01:15

Problem 15

What are the values of input ready and output ready and control bits $F_1$ through $F_4$ in Fig. 11-9 when:
a. The buffer is empty?
b. The buffer is full?
c. The buffer contains two data items?

Ajay Singhal

Numerade Educator

Problem 16

Show a block diagram similar to Fig. 11-10 for the data transfer from a CPU to an interface and then to an $\mathrm{I} / \mathrm{O}$ device. Determine a procedure for setting and clearing the flag bit.

Check back soon!

Problem 17

Using the configuration established in Prob. 11-16, obtain a flowchart (similar to Fig. 11-11) for the CPU program to output data.

Check back soon!

02:21

Problem 18

What is the basic advantage of using interrupt-initiated data transfer over transfer under program control without an interrupt?

Sanchit Jain

Numerade Educator

Problem 19

In most computers an interrupt is recognized only after the execution of the instruction. Consider the possibility of acknowledging the interrupt at any time during the execution of the instruction. Discuss the difficulty that may arise.

Check back soon!

Problem 20

What happens in the daisy-chain priority interrupt shown in Fig. 11-12 when device 1 requests an interrupt after device 2 has sent an interrupt request to the CPU but before the CPU responds with the interrupt acknowledge?

Check back soon!

01:26

Problem 21

Consider a computer without priority interrupt hardware. Any one of many sources can interrupt the computer, and any interrupt request results in storing the return address and branching to a common interrupt routine. Explain how a priority can be established in the interrupt service program.

James Kiss

Numerade Educator

02:11

Problem 22

Using combinational circuit design techniques, derive the Boolean expressions listed in Table 11-2 for the priority encoder. Draw the logic diagram of the circuit.

Adriano Chikande

Numerade Educator

Problem 23

Design a parallel priority interrupt hardware for a system with eight interrupt sources.

Check back soon!

00:57

Problem 24

Obtain the truth table of an $8 \times 3$ priority encoder. Assume that the three outputs $x y z$ from the priority encoder are used to provide a vector address of the form $101 x y z 00$. List the eight vector addresses starting from the one with the highest priority.

Heather Zimmers

Numerade Educator

Problem 25

What should be done in Fig. 11-14 to make the four VAD values equal to the binary equivalent of $76,77,78$, and 79 ?

Check back soon!

Problem 26

What programming steps are required to check when a source interrupts the computer while it is still being serviced by a previous interrupt request from the same source?

Check back soon!

Problem 27

Why are the read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs? Under what condition and for what purpose are they used as outputs?

Check back soon!

01:29

Problem 28

It is necessary to transfer 256 words from a magnetic disk to a memory section starting from address 1230 . The transfer is by means of DMA as shown in Fig. 11-18.
a. Give the initial values that the CPU must transfer to the DMA controller.
b. Give the step-by-step account of the actions taken during the input of the first two words.

James Kiss

Numerade Educator

01:29

Problem 29

A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?

James Kiss

Numerade Educator

Problem 30

Why does DMA have priority over the CPU when both request a memory transfer?

Check back soon!

Problem 31

Draw a flowchart similar to the one in Fig. 11-20 that describes the CPU-I/O channel communication in the IBM 370.

Check back soon!

03:17

Problem 32

The address of a terminal connected to a data communication processor consists of two letters of the alphabet or a letter followed by one of the 10 numerals. How many different addresses can be formulated.

Aaron Goree

Numerade Educator

01:00

Problem 33

List a possible line procedure and the character sequence for the communication between a data communication processor and a remote terminal. The processor inquires if the terminal is operative. The terminal responds with yes or no. If the response is yes, the processor sends a block of text.

James Kiss

Numerade Educator

03:58

Problem 34

A data communication link employs the character-controlled protocol with data transparency using the DLE character. The text message that the transmitter sends between STX and ETX is as follows:
DLE STX DLE DLE ETX DLE DLE ETX DLE ETX
What is the binary value of the transparent text data?

Alex Roush

Numerade Educator

Problem 35

What is the minimum number of bits that a frame must have in the bitoriented protocol?

Check back soon!

05:00

Problem 36

Show how the zero insertion works in the bit-oriented protocol when a zero followed by the 10 bits that represent the binary equivalent of 1023 are transmitted.

James Chok

Numerade Educator